1.

General description

The HEF4021B is an 8-bit static shift register (parallel-to-serial converter) with a

synchronous serial data input (DS), a clock input (CP), an asynchronous active HIGH

parallel load input (PL), eight asynchronous parallel data inputs (D0 to D7) and buffered

parallel outputs from the last three stages (Q5 to Q7).

Each register stage is a D-type master-slave flip-flop with a set direct (SD) and clear direct

(CD) input. Information on D0 to D7 is asynchronously loaded into the register while PL is

HIGH, independent of CP and DS. When PL is LOW, data on DS is shifted into the first

register position and all the data in the register is shifted one position to the right on the

LOW-to-HIGH transition of CP. Schmitt trigger action makes the clock input highly tolerant

of slower rise and fall times.

also suitable for use over both the industrial (

−40 °C to +85 °C) and automotive (−40 °Cto

+125

°C) temperature ranges.

2.

Features

3.

Applications

HEF4021B

8-bit static shift register

Rev. 04 — 10 November 2008

Product data sheet