HEF4094B datasheet(7/17 Pages) NXP

7 / 17 page

HEF4094B_4

Product data sheet

Rev. 04 — 30 October 2008

7 of 17

NXP Semiconductors

HEF4094B

8-stage shift-and-store bus register

[1]

The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).

tPZH

OFF-state to HIGH

propagation delay

OE to QPn;

see Figure 8

5 V

MHz

10 V

MHz

15 V

MHz

tPZL

OFF-state to LOW

propagation delay

OE to QPn;

see Figure 8

5 V

MHz

10 V

MHz

15 V

MHz

tPHZ

HIGH to OFF-state

propagation delay

OE to QPn;

see Figure 8

5 V

150

MHz

10 V

MHz

15 V

MHz

tPLZ

LOW to OFF-state

propagation delay

OE to QPn;

see Figure 8

5 V

160

MHz

10 V

MHz

15 V

MHz

tsu

set-up time

D to CP;

see Figure 9

5 V

10 V

15 V

hold time

D to CP;

see Figure 9

5 V

−15

10 V

15 V

pulse width

minimum LOW

clock pulse;

see Figure 6

5 V

10 V

15 V

minimum HIGH

strobe pulse;

see Figure 7

5 V

10 V

15 V

fmax

maximum frequency

see Figure 6

5 V

MHz

10 V

MHz

15 V

MHz

Table 7.

Dynamic characteristics …continued

VSS = 0 V; Tamb = 25 °C; for test circuit see Figure 10; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

VDD

Extrapolation formula

Min

Typ

Max

Unit

Table 8.

Dynamic power dissipation

VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C.

Symbol

Parameter

VDD

Typical formula for PD (µW)

where:

dynamic power

dissipation

5 V

PD = 2100 × fi + Σ(fo × CL) × VDD2

fi = input frequency in MHz,

fo = output frequency in MHz,

CL = output load capacitance in pF,

VDD = supply voltage in V,

Σ(CL × fo) = sum of the outputs.

10 V

PD = 9700 × fi + Σ(fo × CL) × VDD2

15 V

PD = 26000 × fi + Σ(fo × CL) × VDD2

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