PCF8562TTSLASHS400SLASH2 datasheet(13/36 Pages) NXP

13 / 36 page

PCF8562_3

Product data sheet

Rev. 3 — 2 December 2008

13 of 36

NXP Semiconductors

PCF8562

Universal LCD driver for low multiplex rates

7.5 Oscillator

7.5.1 Internal clock

The internal logic of the PCF8562 and its LCD drive signals are timed either by its internal

oscillator or by an external clock. The internal oscillator is enabled by connecting pin OSC

to pin VSS. After power-on, pin SDA must be HIGH to guarantee that the clock starts.

7.5.2 External clock

Pin CLK is enabled as an external clock input by connecting pin OSC to VDD.

The LCD frame signal frequency is determined by the clock frequency (fclk).

A clock signal must always be supplied to the device; removing the clock freezes the LCD

in a DC state.

7.6 Timing

The PCF8562 timing controls the internal data ﬂow of the device. This includes the

transfer of display data from the display RAM to the display segment outputs. The timing

also generates the LCD frame signal whose frequency is derived from the clock

frequency. The frame signal frequency is a ﬁxed division of the clock frequency from either

the internal or an external clock:

7.7 Display register

The display latch holds the display data while the corresponding multiplex signals are

generated. There is a one-to-one relationship between the data in the display latch, the

LCD segment outputs and each column of the display RAM.

7.8 Segment outputs

The LCD drive section includes 32 segment outputs S0 to S31 which should be

connected directly to the LCD. The segment output signals are generated in accordance

with the multiplexed backplane signals and with data residing in the display latch. When

less than 32 segment outputs are required, the unused segment outputs should be left

open-circuit.

7.9 Backplane outputs

The LCD drive section includes four backplane outputs BP0 to BP3 which must be

connected directly to the LCD. The backplane output signals are generated in accordance

with the selected LCD drive mode. If less than four backplane outputs are required, the

unused outputs can be left open-circuit.

In the 1:3 multiplex drive mode, BP3 carries the same signal as BP1, therefore these two

adjacent outputs can be tied together to give enhanced drive capabilities.

In the 1:2 multiplex drive mode, BP0 and BP2, BP1 and BP3 all carry the same signals

and may also be paired to increase the drive capabilities.

In the static drive mode the same signal is carried by all four backplane outputs and they

can be connected in parallel for very high drive requirements.

clk

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