CMS3216LAH datasheet(22/46 Pages) FIDELIX

22 / 46 page

Rev0.2, Jan. 2007

CMS3216LAx-75xx

A Read Burst can be terminated by a subsequent Write com-

mand, and data from a fixed length READ burst may be

immediately followed by data from a WRITE command (subject

to bus turnaround limitations). The WRITE burst may be

initiated on the clock edge immediately following the last (or last

desired) data element from the READ burst, provided that I/O

contention can be avoided. In a given system design, there may

be a possibility that the device driving the input data will go

Low-Z before the SDRAM DQs go High-Z. In this case, at least

a single-cycle delay should occur between the last read data

and the WRITE command. The DQM input is used to avoid I/O

contention, as shown in Figure 6. and Figure 7. . The DQM

signal must be asserted (HIGH) at least two clocks prior to the

WRITE command (DQM latency is two clocks for output buffers)

to suppress data-out from the READ. Once the WRITE comma-

nd is registered, the DQs will go High-Z (or remain High-Z),

regardless of the state of the DQM signal, provided the DQM

Figure 5. Random Read Accesses for CAS Latency =1,2,3

CAS Latency=2

CLK

Command

Address

Dout

Read

NOP

Bank

Col n

CAS Latency=3

CLK

Command

Address

Dout

Read

NOP

Bank

Col n

NOP

Bank

Col a

Bank

Col x

Bank

Col m

Bank

Col a

Bank

Col x

Bank

Col m

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