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ST72371 Datenblatt(PDF) 30 Page - STMicroelectronics |
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ST72371 Datenblatt(HTML) 30 Page - STMicroelectronics |
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30 / 94 page ![]() 30/94 ST72371/ST72372 4.2 WATCHDOG TIMER (WDG) 4.2.1 Introduction The Watchdog timer is used to detect the occur- rence of a software fault, usually generated by ex- ternal interference or by unforeseen logical condi- tions, which causes the application program to abandon its normal sequence. The Watchdog cir- cuit generates an MCU reset on expiry of a pro- grammed time period, unless the program refresh- es the counter’s contents before the T6 bit be- comes cleared. 4.2.2 Main Features s Programmable timer (64 increments of 49,152 CPU cycles) s Programmable reset s Reset (if watchdog activated) after a HALT instruction or when the T6 bit reaches zero Figure 16. Watchdog Block Diagram RESET WDGA 7-BIT DOWNCOUNTER fCPU T6 T0 CLOCK DIVIDER WATCHDOG CONTROL REGISTER (CR) ÷ 49152 T1 T2 T3 T4 T5 |
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