W.A.R.P. TIMING TABLES

Off-line Phase Timing (Internal RAMs Loading with Charge Mode ”0”)

OF L

I0 - I6

DATA 0

D ATAn

DATA 1

MC L K

FIN

NP

EP

F IN d e t e c t io n

D AT A 0 a c q u i s iti o n

D AT A 1 a c q u i s iti o n

D ATA n a c q u is it io n

Timing Table Description: OFF-LINE phase (CHM ”0”)

- CHM [INPUT] low will enable the ’manual downloading’ by specifying the address and data to be loaded

into W.A.R.P..

- MCLK [INPUT] must be connected with the external synchronization signal.

- PRST [INPUT] must be set high to enable the device.

- OFL [INPUT] must be set high to enable the configurationloading phase into the internal RAMs of W.A.R.P..

- The input to be written into the internal memories at the address specified in A0-A9 must be put into I0-I7

bus .

- SYNC [OUTPUT] will be provided to synchronize input data (I0-I7,A0-A9) coming from an external

new data and address that must be given within next 31MCLK pulses. Afterwards W.A.R.P. stores the data

on input buses and restores a new SYNC pulse.

W.A.R.P. stores the data situated in I0-I7 and the addresses A0-A9 into its internal registers.

Figure 8.

Block Diagram for W.A.R.P. downloading (CHM ”0”)

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