INA8583

One data bit is transferred during each clock pulse. The data on the SDA line must remain stable

during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted

as a control signal.

.

Bit transfer

SDA

SCL

Data

change

valid

of data

allowed

Fig. 4.

Both SDA and SCL lines remain HIGH when the bus is not busy. The HIGH-to-LOW tran-

sition of the data line, while the clock is High is defined as the start condition (S). A LOW-to-HIGH

transition of the data line while the clock is HIGH is defined as the stop condition (Р).

Definition of start and stop conditions.

SDA

SCL

S

P

Fig. 5.

A device generating a message is a “transmitter” a device receiving a message is a “re-

ceiver”. The device that controls the message is the “master”, and the devices which are controlled

by the master are “slaves”.

The number of data bytes transferred between the start and stop conditions from the trans-

mitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge bit.

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