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LT1801/LT1802

18012fb

APPLICATIO S I FOR ATIO

Circuit Description

The LT1801/LT1802 have an input and output signal range

that covers from the negative power supply to the positive

power supply. Figure 1 depicts a simplified schematic of

the amplifier. The input stage is comprised of two differ-

ential amplifiers, a PNP stage Q1/Q2 and an NPN stage Q3/

Q4 that are active over the different ranges of common

mode input voltage. The PNP differential pair is active

between the negative supply to approximately 1.2V below

the positive supply. As the input voltage moves closer

toward the positive supply, the transistor Q5 will steer the

tail current I1 to the current mirror Q6/Q7, activating the

NPN differential pair and the PNP pair becomes inactive

for the rest of the input common mode range up to the

positive supply. Also at the input stage, devices Q17 to

Q19 act to cancel the bias current of the PNP input pair.

When Q1-Q2 are active, the current in Q16 is controlled to

be the same as the current in Q1-Q2, thus the base current

of Q16 is nominally equal to the base current of the input

devices. The base current of Q16 is then mirrored by

devices Q17-Q19 to cancel the base current of the input

devices Q1-Q2.

A pair of complementary common emitter stages Q14/

Q15 that enable the output to swing from rail to rail

constructs the output stage. The capacitors C2 and C3

form the local feedback loops that lower the output imped-

ance at high frequency. These devices are fabricated on

Linear Technology’s proprietary high speed complemen-

tary bipolar process.

Power Dissipation

The LT1801 amplifier is offered in a small package, SO-8,

which has a thermal resistance of 190

°C/W, θJA. So there

is a need to ensure that the die’s junction temperature

should not exceed 150

°C. Junction temperature TJ is

calculated from the ambient temperature TA, power dissi-

pation PD and thermal resistance θJA:

TJ = TA + (PD • θJA)

The power dissipation in the IC is the function of the supply

voltage, output voltage and the load resistance. For a given

supply voltage, the worst-case power dissipation PDMAX

occurs at the maximum supply current and the output

Figure 1. LT1801/LT1802 Simplified Schematic Diagram

Q18

Q17

Q16

Q10

Q13

Q15

OUT

Q11

Q12

VBIAS

ESDD2

ESDD1

+IN

–IN

V–

ESDD3

ESDD4

V+

V–

Q14

18012 F01

V–

BUFFER

AND

OUTPUT BIAS

V+

V–

Q19

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