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TC7129CPL Datenblatt(PDF) 13 Page - TelCom Semiconductor, Inc

Teilenummer TC7129CPL
Bauteilbeschribung  4-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTER WITH ON-CHIP LCD DRIVERS
PDF  15 Pages
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Hersteller  TELCOM [TelCom Semiconductor, Inc]
Direct Link  http://www.telcom-semi.com
Logo TELCOM - TelCom Semiconductor, Inc

TC7129CPL Datenblatt(HTML) 13 Page - TelCom Semiconductor, Inc

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TELCOM SEMICONDUCTOR, INC.
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TC7129
4-1/2 DIGIT ANALOG-TO-DIGITAL
CONVERTER WITH ON-CHIP LCD DRIVERS
Figure 13.
Integrator Block Diagram
The buffer amplifier has a common-mode input voltage
range from 1.5V above Vto 1V below V+. The integrator
amplifier can swing to within 0.3V of the rails, although for
best linearity the swing is usually limited to within 1V. Both
amplifiers can supply up to 80
µA of output current, but
should be limited to 20
µA for good linearity.
Continuity Indicator
A comparator with a 200 mV threshold is connected
between IN HI (pin 33) and IN LO (pin 32). Whenever the
voltage between inputs is less than 200 mV, the
CONTINUITY output (pin 27) will be pulled HIGH, activating
the continuity annunciator on the display. The continuity
pin can also be used as an input to drive the continuity
annunciator directly from an external source. A schematic
of the input/output nature of this pin is shown in Figure 15.
Figure 14.
Continuity Indicator Circuit
COM
BUFFER
200 mV
IN HI
+
IN LO
+
V
CONT
500 k
TO DISPLAY
DRIVER
(NOT LATCHED)
TC7129
COMMON
REF HI
BUFFER
INTE-
GRATOR
DE
ZI, X10
COMPARATOR 1
200 mV
CREF
RINT
CINT
INT1
IN HI
+
+
+
REF LO
DE
IN LO
+
DE–
DE+
DE+
DE–
100 pF
V
+
CONTINUITY
INT1, INT2
CONTINUITY
COMPARATOR
500 k
REST
TO DISPLAY DRIVER
10
pF
COMPARATOR 2
TO DIGITAL
SECTION
TC7129
INT
X10
Table I. Switch Legends
Label
Meaning
DE
Open during all deintegrate phases.
DE–
Closed during all deintegrate phases when input
voltage is negative.
DE+
Closed during all deintegrate phases when input
voltage is positive.
INT1
Closed during the first integrate phase
(measurement of the input voltage).
INT2
Closed during the second integrate phase
(measurement of the amplifier offset).
INT
Open during both integrate phases.
REST
Closed during the rest phase.
ZI
Closed during the zero-integrate phase.
X10
Closed during the X10 phase.
X10
Open during the X10 phase.



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