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AX2000-1CS896I Datenblatt(PDF) 33 Page - Actel Corporation |
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AX2000-1CS896I Datenblatt(HTML) 33 Page - Actel Corporation |
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33 / 226 page ![]() Axcelerator Family FPGAs v2.7 2-19 I/O Standard Electrical Specifications Table 2-18 • Input Capacitance Symbol Parameter Conditions Min. Max. Units CIN Input Capacitance VIN=0, f=1.0 MHz 10 pF CINCLK Input Capacitance on Clock Pin VIN=0, f=1.0 MHz 10 pF Figure 2-9 • Input Buffer Delays Figure 2-10 • Output Buffer Delays Y IN INBUF PAD ln Y GND Input High 0V V CCA t DP t DP Vtrip Vtrip 50% 50% (Rising) (Falling) ln ln Out GND 50% 50% TRIBUF En En Out GND 50% 10% 50% En Out GND 50% 50% 90% To AC test loads (shown below) OUT Pad VTT tENHZ tENHZ VOH Vtrip GND/VTT VTT VOL tENLZ tENLZ VCCI/VTT Vtrip Vtrip Vtrip VOH tPY tPY (tDLH) (tDHL) VCCA VCCA VCCA VOL |
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