LTC1654IGN datasheet(6/16 Pages) LINER

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LTC1654

1654fb

CS/LD (Pin 5): The TTL Level Input for the Serial Interface

Enable and Load Control. When CS/LD is low, the SCK

signal is enabled, so the data can be clocked in. When

CS/LD is pulled high, the control/address bits are

decoded.

DGND/AGND (Pins 6, 12): Digital and Analog Grounds.

SDO (Pin 7): The output of the shift register that becomes

valid on the rising edge of the serial clock.

VOUT A/B (Pins 9, 15): The Buffered DAC Outputs.

REFHI A/B (Pins 10, 14): The Reference High Inputs of the

LTC1654. There is a gain of 1 from this pin to the output

in a gain of 1 configuration. In a gain of 1/2 configuration,

there is a gain of 1/2 from this pin to VOUT.

REFLO A/B (Pins 11, 13): The Reference Low Inputs of the

LTC1654. These inputs can swing up to VCC – 1.5V.

VCC (Pin 16): The Positive Supply Input. 2.7V ≤ VCC ≤ 5.5V.

Requires a 0.1

µF bypass capacitor to ground.

X1/X1/2 B, X1/X1/2 A (Pins 1, 8): The Gain of 1 or Gain of

1/2 Pin. When this pin is tied to VOUT, the output range will

be REFLO to (REFLO + REFHI)/2 (0V to REFHI/2 when

REFLO = 0V). When this pin is tied to REFLO, the output

range will be REFLO to REFHI (0V to REFHI when REFLO

= 0V). These pins should not be left floating.

CLR (Pin 2): The Asynchronous Clear Input.

SCK (Pin 3): The TTL Level Input for the Serial Interface

Clock.

SDI (Pin 4): The TTL Level Input for the Serial Interface

Data. Data on the SDI pin is latched into the shift register

on the rising edge of the serial clock. The LTC1654 allows

either a 24-bit or 32-bit word. When a 24-bit word is used,

the first 8 bits are control and address followed by 16 data

bits. The last two of the 16 data bits are don’t cares. When

a 32-bit word (required for daisy-chain operation) is used,

the first 8-bits are don’t cares and the following 24-bits are

as above.

1654 TD01

CURRENT WORD

SCK

CS/LD

SDI

SDO

(PREVIOUS

WORD)

TI I G DIAGRA S

PI FU CTIO S

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