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LTC1741IFW Datenblatt(PDF) 8 Page - Linear Technology |
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LTC1741IFW Datenblatt(HTML) 8 Page - Linear Technology |
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8 / 20 page ![]() 8 LTC1741 1741f PI FU CTIO S SENSE (Pin 1): Reference Sense Pin. Ground selects ±1V. VDD selects ±1.6V. Greater than 1V and less than 1.6V applied to the SENSE pin selects an input range of ±VSENSE, ±1.6V is the largest valid input range. VCM (Pin 2): 2.35V Output and Input Common Mode Bias. Bypass to ground with 4.7 µF ceramic chip capacitor. GND (Pins 3, 6, 9, 12, 13, 16, 19, 21, 36, 37): ADC Power Ground. AIN+ (Pin 4): Positive Differential Analog Input. AIN– (Pin 5): Negative Differential Analog Input. VDD (Pins 7, 8, 17, 18, 20): 5V Supply. Bypass to AGND with 1 µF ceramic chip capacitors. REFLB (Pin 10): ADC Low Reference. Bypass to Pin 11 with 0.1 µF ceramic chip capacitor. Do not connect to Pin 14. REFHA (Pin 11): ADC High Reference. Bypass to Pin 10 with 0.1 µFceramicchipcapacitor,toPin14witha4.7µFceramic capacitor and to ground with 1 µF ceramic capacitor. REFLA (Pin 14): ADC Low Reference. Bypass to Pin 15 with 0.1 µF ceramic chip capacitor, to Pin 11 with a 4.7µF ce- ramic capacitor and to ground with 1 µF ceramic capacitor. REFHB (Pin 15): ADC High Reference. Bypass to Pin 14 with 0.1 µF ceramic chip capacitor. Do not connect to Pin 11. MSBINV (Pin 22): MSB Inversion Control. Low inverts the MSB, 2’s complement output format. High does not invert the MSB, offset binary output format. ENC (Pin 23): Encode Input. The input sample starts on the positive edge. ENC (Pin 24): Encode Complement Input. Conversion starts on the negative edge. Bypass to ground with 0.1 µF ceramic for single-ended ENCODE signal. OE (Pin 25): Output Enable. Low enables outputs. Logic high makes outputs Hi-Z. OE should not exceed the voltage on 0VDD. CLKOUT (Pin 26): Data Valid Output. Latch data on the rising edge of CLKOUT. OGND (Pins 27, 38, 47): Output Driver Ground. NC (Pins 28, 29): Do not connect these pins. D0-D1 (Pins 30 to 31): Digital Outputs. OVDD (Pins 32, 43): Positive Supply for the Output Driv- ers. Bypass to ground with 0.1 µF ceramic chip capacitor. D2-D4 (Pins 33 to 35): Digital Outputs. D5-D8 (Pins 39 to 42): Digital Outputs. D9-D11 (Pins 44 to 46): Digital Outputs. OF (Pin 48): Over/Under Flow Output. High when an over or under flow has occurred. |
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