SN54F20, SN74F20

DUAL 4-INPUT POSITIVE-NAND GATES

SDFS041A – MARCH 1987 – REVISED OCTOBER 1993

Copyright

2–1

POST OFFICE BOX 655303

Small-Outline Packages, Ceramic Chip

Carriers, and Standard Plastic and Ceramic

300-mil DIPs

description

These devices contain two independent 4-input

NAND gates. They perform the Boolean functions

Y = A

• B • C • D or Y = A + B + C + D in positive

logic.

The SN54F20 is characterized for operation over

the full military temperature range of – 55

°C to

125

°C. The SN74F20 is characterized for

operation from 0

°C to 70°C.

FUNCTION TABLE

(each gate)

INPUTS

OUTPUT

A

B

C

D

Y

H

H

H

H

L

L

XX

X

H

X

LX

X

H

X

XL

X

H

X

X

X

L

H

&

1Y

6

2Y

8

1

1A

2

1B

4

1C

5

1D

9

2A

10

2B

12

2C

13

2D

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the D, J, and N packages.

logic diagram, each gate (positive logic)

Y

A

B

C

D

SN54F20 ...J PACKAGE

SN74F20 ...D OR N PACKAGE

(TOP VIEW)

SN54F20 . . . FK PACKAGE

(TOP VIEW)

32

1 20 19

910 11 12 13

4

5

6

7

8

18

17

16

15

14

2C

NC

NC

NC

2B

NC

NC

1C

NC

1D

NC – No internal connection

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1A

1B

NC

1C

1D

1Y

GND

2D

2C

NC

2B

2A

2Y

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.