CDK1303 datasheet(8/9 Pages) CADEKA

8 / 9 page

www.cadeka.com

Data Sheet

Operation

The CDK1303 has 256 preamp/comparator pairs which are

each supplied with the voltage from VRT to VRB divided

equally by the resistive ladder as shown in the block

diagram. This voltage is applied to the positive input of

each preamplifier/comparator pair. An analog input volt-

age applied at VIN is connected to the negative inputs of

each preamplifier/comparator pair. The comparators are

then clocked through each one’s individual clock buffer.

When the CLK pin is in the low state, the master or input

stage of the comparators compare the analog input volt-

age to the respective reference voltage. When the CLK

pin changes from low to high the comparators are latched

to the state prior to the clock transition and output logic

codes in sequence from the top comparators, closest to

VRT (0V), down to the point where the magnitude of the

input signal changes sign (thermometer code). The output

of each comparator is then registered into four 64-to-6

bit decoders when the CLK is changed from high to low.

At the output of the decoders is a set of four 7-bit latches

which are enabled (“track”) when the clock changes from

high to low. From here, the output of the latches are

coded into 6 LSBs from 4 columns and 4 columns are coded

into 2 MSBs. Finally, 8 ECL output latches and buffers

are used to drive the external loads. The conversion

takes one clock cycle from the input to the data outputs.

Figure 2. Timing Diagram

VIN

CLK

DRA

DRB

Data Bank B

N-1

N+1

N+3

N+1

N+2

N+3

N+4

N+5

N+6

N+7

N-2

N+2

N+4

Data Bank A

1.4 ns typ

1.75 ns typ

1.0 ns

1.75 ns typ

CDK1303 Datenblatt(PDF) 8 Page - Cadeka Microcircuits LLC.

CDK1303 Datenblatt(HTML) 8 Page - Cadeka Microcircuits LLC.

Html Pages

1 2 3 4 5 6 7 8 9

Datenblatt Download

Link URL