©2009 CADEKA Microcircuits LLC

www.cadeka.com

13

PRELIMINARY Data Sheet

Digital and Timing Electrical Characteristics

(AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, unless otherwise noted)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

Clock Inputs

Duty Cycle

20

80

%high

Compliance

CMOS, LVDS, LVPECL

Input range

Differential input swing

200

200

Input range

Differential input swing, sine wave clock input

800

800

Input common mode voltage

Keep voltages within gnd and voltage of AVDD

0.3

V

Input capacitance

Differential

2

pF

Logic Inputs (CMOS)

High Level Input Voltage

2

V

V

Low Level Input Voltage

0

0.8

V

0

V

High Level Input Leakage Current

-10

10

μA

Low Level Input Leakage Current

-10

10

μA

Input Capacitance

3

pF

Data Outputs (LVDS)

Compliance

LVDS

Digital Output Voltage

247

454

mV

Output Common Mode Voltage

1.125

1.375

V

Output Coding

Default/Optional

Offset Binary/2‘s Complement

Timing Characteristics

Aperture Delay

0.8

ns

Aperture Jitter

<0.5

ps

Power Down

Start up time from Power Down to Active

Mode. References have reached 99% of final

value. (See section Clock Frequency)

350

900

clock

cycles

Sleep Mode

Start up time from Sleep Mode to Active Mode

0.5

μs

Out Of Range Recovery Time

1

clk cycles

Pipeline Delay

14

clk cycles

LVDS Output Timing Characterisctics

LCLK to Data Delay Time

Excluding programmable phase shift

50

ps

Clock Propagation Delay

TBD

ns

LVDS Bit-Clock Duty-Cycle

45

55

% LCLK

cycle

Frame clock cycle-to-cycle jitter

2.5

% LCLK

cycle

Data Rise- and Fall Time

Calculated from -100mV to +100mV,

and vice-versa

TBD

ns

Clock Rise- and Fall Time

Calculated from -100mV to +100mV,

and vice-versa

TBD

ns

Note:

(1) The outputs will be functional with higher loads. However, it is recommended to keep the load on output data bits as low as possible to keep dynamic currents

and resulting switching noise at a minimum.