AD Conversion Timing (at ADIN (ADC) Input Mode 1 Register D5=1)

These figures are shown when the Mode 1 D8 bit is set to “1”, and an external clock is input to the OUTCK pin. When setting

D8 bit to “0”, the ADCLK is used as OUTCK.

Note : At default condition in ADIN mode, data are sampled at the falling edge of the ADCK clock, and are output at the rising

edge of the OUTCK clock. Set the ADCLK polarity register to “1” when the data are sampled and are output at the falling

edge of the ADCK clock.

The diagram on the upper portion of this page shows the default timing and the lower left figure shows the inverted timing

Delay from data sampling to data output

ADCLK normal : At Mode 1 register D6=0; 5.5 clk delay

ADCLK inversion : At Mode 1 register D6=1; 6.0 clk delay

In ADIN input mode, the above mentioned register setting is available.

At ADIN (PGA) input Mode 1 register D5=0 and D4=1, digital data output is delayed by 2 clks.

ADCLK Clock Waveform

A

13

ADCLK Inversion Chart

ADCK

ADCK Input

Rising Edge

Sampling Point

N

N+1

OUTCK Timing Chart

ADCK

OUTCK

ADC Direct Input Chart

ADCLK

ADCLK Input

OUTCK

Digital Output

N-2

N-1

N

N-6

N-5

N+4

N+5

N+6

N

N+1

Falling Edge