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T221160A Datenblatt(PDF) 5 Page - Taiwan Memory Technology |
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T221160A Datenblatt(HTML) 5 Page - Taiwan Memory Technology |
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5 / 14 page ![]() TE CH tm T221160A Taiwan Memory Technology, Inc. reserves the right P. 5 Publication Date: FEB. 2002 to change products or specifications without notice. Revision:A AC CHARACTERISTICS (note 1,2,3) (Ta = 0 to 70°C) AC TEST CONDITIONS: Vcc=5V ±10%, input pulse level = 0 to 3V Input rise and fall times: 2ns Output Load: 2TTL gate + CL (50pF) -25 -30 -35 -40 AC CHARACTERISTICS PARAMETER SYM MIN MAX MIN MAX MIN MAX MIN MAX UNIT Notes Read or Write Cycle Time tRC 43 55 65 75 ns Read-Modify-Write Cycle Time tRWC 65 85 95 105 ns Fast-Page-Mode Read or Write Cycle Time tPC 15 20 23 25 ns Fast-Page-Mode Read-Write Cycle Time tPCM 37 42 49 52 ns Access Time From RAS tRAC 25 30 35 40 ns 4 Access Time From CAS tCAC 7 8 9 10 ns 5 Access Time From OE tOAC 7 8 9 10 ns 13 Access Time From Column Address tAA 12 16 18 20 ns 8 Access Time From CAS Precharge tACP 14 18 20 22 ns RAS Pulse Width tRAS 25 10K 30 10K 35 10K 40 10K ns RAS Pulse Width tRASC 25 100K 30 100K 35 100K 40 100K ns RAS Hold Time tRSH 7 8 9 10 ns RAS Precharge Time tRP 15 20 23 25 ns CAS Pulse Width tCAS 4 10K 6 10K 8 10K 10 10K ns CAS Hold Time tCSH 21 26 30 35 ns CAS Precharge Time tCP 3 3 4 5 ns RAS to CAS Delay Time tRCD 10 17 10 21 10 25 10 29 ns 7 CAS to RAS Precharge Time tCRP 3 3 3 5 ns Row Address Setup Time tASR 0 0 0 0 ns Row Address Hold Time tRAH 5 5 5 5 ns RAS to Column Address Delay Time tRAD 8 13 8 14 8 16 8 18 ns 8 Column Address Setup Time tASC 0 0 0 0 ns Column Address Hold Time tCAH 4 4 4 5 ns Column Address Hold Time (Reference to RAS ) tAR 22 26 30 34 ns Column Address to RAS Lead Time tRAL 12 14 16 18 ns Read Command Setup Time tRCS 0 0 0 0 ns 14 Read Command Hold Time Reference to CAS tRCH 0 0 0 0 ns 9,14 Read Command Hold Time Reference to RAS tRRH 0 0 0 0 ns 9 CAS to Output in Low-Z tCLZ 3 3 3 3 ns Output Buffer Turn-off Delay From CAS or RAS tOFF1 3 15 3 15 3 15 3 15 ns 10,16 |
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