TMC2193 datasheet(7/72 Pages) CADEKA

7 / 72 page

PRODUCT SPECIFICATION

TMC2193

REV. 1.0 3/26/03

Functional Description

Input Formats

Control Registers for this section

The TMC2193 supports both RGB and YCBCR component

sources on the pixel data port. For RGB sources the

TMC2193 will accept a 24 bit RGB source with a sample

rate of 4:4:4. YCBCR input sources are supported in 10 bit

4:2:2, 20 bit 4:2:2, 20 bit 4:4:4, and 24 bit 4:4:4. In the 4:2:2

cases the color difference components are linearly interpo-

lated to 4:4:4 internally.

Demuxing of multiplexed data streams depends on which

synchronization mode the encoder is operating in. For slave

and genlock modes the falling edge of HSIN must be LOW

prior to the CB data in order to demux the data correctly. For

master mode synchronization the falling edge of HSOUT

must be LOW prior to the Y data in order to demux the data

correctly. Finally, in 656 mode the demuxing of the data

stream is determined by the TRS codes, the ﬁrst sample after

the TRS is considered a CB sample of the CB Y CR YI

packet.

The control register D1OFF controls the formatting of the

incoming luminance data at the pixel data port. When

D1OFF is HIGH a blanking level of 6410 is subtracted from

the luminance and when D1OFF is LOW the incoming the

pixel data is passed through. The inversion of the MSB’s on

the CB and CR components is controlled by the INMODE

control register.

Figure 1. Input Formats

INMODE = 000 or 100, PD[7:0] = Y/G, PD[23:16] = CB/B, PD[15:8] = CR/R

Figure 2. 24 Bit Input Format

Address

Bit(s)

Name

0x05

D1OFF

0x05

6-4

INMODE

0x06

TSOUT

INMODE

x00

101

110

111

65-6294-02

7CB/BLUE

CR/RED

Y/GREEN

9YCBCR

9CBCR

tDO

PD[7:0]

PD[15:8]

PD[23:16]

PXCK

HSOUT

(TSOUT = 1)

65-6294-03

(Y/G)n-1

(C /R)

n-1

(C /B)

n-1

(Y/G)x+1

(Y/G)x+2

(Y/G)x

(Y/G)n

(Y/G)0

(C /R)

(C /B)

tDO

x = (SY+BR+BU+CBP)*2

128

n = (SY+BR+BU+CBP+AV)*2

HSIN

tSP

(C /B)

x+1

(C /B)

x+2

(C /R)

x+1

(C /R)

x+2

INMODE = 101, PD[23:14] = YCBCR running at 27MHz.

The PD port is clocked at twice the pixel rate, with the data

organized as CB Y CR Y, with the cosited Y's following the

CB's. In its CCIR-656 time base mode, the demuxed CB, Y,

and CR data is synchronized to the SAV preamble. The ﬁrst

data value, after the SAV preamble, is treated as a CB data

point in the multiplexed CB, Y, CR Y , D1 data stream.

Note: Figure 3, pixel numbering, reﬂects the SMPTE-125M

pixel numbering.

TMC2193 Datenblatt(PDF) 7 Page - Cadeka Microcircuits LLC.

TMC2193 Datenblatt(HTML) 7 Page - Cadeka Microcircuits LLC.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

Datenblatt Download

Link URL