CS2100-CP_09 datasheet(10/32 Pages) CIRRUS

10 / 32 page

CS2100-CP

DS840F1

CONTROL PORT SWITCHING CHARACTERISTICS - SPI FORMAT

Inputs: Logic 0 = GND; Logic 1 = VD; CL =20pF.

Notes: 13. tspi is only needed before first falling edge of CS after power is applied. tspi = 0 at all other times.

14. Data must be held for sufficient time to bridge the transition time of CCLK.

15. For fcclk < 1 MHz.

Parameter

Symbol

Min

Max

Unit

CCLK Clock Frequency

fccllk

-6

MHz

CCLK Edge to CS Falling

(Note 13)tspi

500

CS High Time Between Transmissions

tcsh

1.0

µs

CS Falling to CCLK Edge

tcss

CCLK Low Time

tscl

CCLK High Time

tsch

CDIN to CCLK Rising Setup Time

tdsu

CCLK Rising to DATA Hold Time

(Note 14)tdh

Rise Time of CCLK and CDIN

(Note 15)tr2

100

Fall Time of CCLK and CDIN

(Note 15)tf2

100

Delay from Supply Voltage Stable to Control Port Ready

tdpor

100

µs

dsu

sch

scl

CCLK

CDIN

css

csh

spi

tdpor

Figure 6. Control Port Timing - SPI Format (Write Only)

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