CS5566

16

DS806PP2

5/4/09

3.3 Clock

The CS5566 can be operated from its internal oscillator or from an external master clock. The state of

MCLK determines which clock source will be used. If MCLK is tied low, the internal oscillator will start and

be used as the clock source for the converter. If an external CMOS-compatible clock is input into MCLK

the converter will power down the internal oscillator and use the external clock. If the MCLK pin is held

high, the internal oscillator will be held in the stopped state. The MCLK input can be held high to delete

clock cycles to aid in operating multiple converters in different phase relationships.

The internal oscillator can be used if the signals to be measured are essentially DC. The internal oscillator

exhibits jitter at about 500 picoseconds rms. If the CS5566 is used to digitize AC signals, an external

low-jitter clock source should be used.

If the internal oscillator is used as the clock for the CS5566, the maximum conversion rate will be dictated

by the oscillator frequency.

If driven from an external MCLK source, the fast rise and fall times of the MCLK signal can result in clock

coupling from the internal bond wire of the IC to the analog input. Adding a 50 ohm resistor on the external

MCLK source significantly reduces this effect.

3.4 Voltage Reference

The voltage reference for the CS5566 can range from 2.4 volts to 4.2 volts. A 4.096 volt reference is re-

quired to achieve the specified performance. Figure 8 and Figure 9 illustrate the connection of the voltage

reference with either a single +5 V analog supply or with ±2.5 V.

For optimum performance, the voltage reference device should be one that provides a capacitor connec-

tion to provide a means of noise filtering, or the output should include some type of bandwidth-limiting fil-

ter. Some 4.096 volt reference devices need only 5 volts total supply for operation and can be connected

as shown in Figure 8 or Figure 9. The reference should have a local bypass capacitor and an appropriate

output capacitor.

Some older 4.096 voltage reference designs require more headroom and must operate from an input volt-

age of 5.5 to 6.5 volts. If this type of voltage reference is used ensure that when power is applied to the

system, the voltage reference rise time is slower than the rise time of the V1+ and V1- power supply volt-

age to the converter. An example circuit to slow the output startup time of the reference is illustrated in

Figure 7.

Figure 7. Voltage Reference Circuit

2k

10

μF

5.5 to 15 V

VIN

VOUT

GND

4.096 V

Refer to V1- and VREF1 pins.