SA53

SA53U

9

P r o d u c t I n n o v a t i o n F r o m

SGND

Gate

Control

Vs

OUT 1

PGND

1t

1b

SC

TEMP

SC

Logic

Temp

Sense

Ref

I1

DIS2

I

UVLO

I1'

Lim 2

+

_

Vdd

Lim 1

Current

Sense

12k

12k

12k

12k

Vth

The block diagram in Figure 5 illustrates the features of the input and output structures of the SA53. For simplicity,

a single phase is shown.

FIgURE5.INPUTANDOUTPUTSTRUCTURESFORASINgLEPhASE

TABLE2.TRUThTABLE

Comments

0 0

X

X

X

High-Z

Top and Bottom output FETs for that phase are turned off.

0 1 <V

th

0

0

PGND

Bottom output FET for that phase is turned on.

1 0 <V

th

0

0

VS

Top output FET for that phase is turned on.

1 1

X

X

X

High-Z

Both output FETs for that phase are turned off.

X X >V

th

1

X

High-Z

Voltage on I1 or I2 has exceeded Vth, which causes I

This internally disables Top and Bottom output FETs for ALL phases.

X X

X

X

1

High-Z

DIS2 pin pulled high, which disables all outputs.

X X

X

Pulled

High X

High-Z

Pulling the I

which disables ALL output FETs.

X X

X

Pulled

Low

0

Determined

by PWM

inputs

Pulling the DIS2 pin low externally disables the cycle-by-cycle current limit

function. The state of the outputs is strictly a function of the PWM inputs.

X X

X

X

X

High-Z

If V