AS5C2568CW-25LSLASH883C datasheet(5/16 Pages) AUSTIN

5 / 16 page

SRAM

MT5C2568

AS5C2568

MT5C2568 / AS5C2568

Rev. 4.5 06/05

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

Austin Semiconductor, Inc.

NOTES

All voltages referenced to V

SS (GND).

-3V for pulse width < 20ns

CC is dependent on output loading and cycle rates.

The

specified value applies with the outputs unloaded, and

f =

Hz.

tRC (MIN)

This parameter is guaranteed but not tested.

Test conditions as specified with the output loading as

shown in Fig. 1 unless otherwise noted.

t HZCE, tHZOE and tHZWE are specified with CL = 5pF

as in Fig. 2. Transition is measured ±500mV typical from

steady state voltage, allowing for actual tester RC time

constant.

At any given temperature and voltage condition, tHZCE

is less than tLZCE, and tHZWE is less than tLZWE.

WE\ is HIGH for READ cycle.

Device is continuously selected. Chip enables and

output enables are held in their active state.

10. Address valid prior to, or coincident with, latest

occurring chip enable.

11. tRC = Read Cycle Time.

12. Chip enable (CE\) and write enable (WE\) can initiate and

terminate a WRITE cycle.

DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)

LOW Vcc DATA RETENTION WAVEFORM

123

1234

DON’T CARE

UNDEFINED

AC TEST CONDITIONS

Input pulse levels....................................................Vss to 3V

Input rise and fall times.....................................................5ns

Input timing reference level.............................................1.5V

Output reference level......................................................1.5V

Output load.................................................See figures 1 & 2

DESCRIPTION

CONDITIONS

SYM

MIN

MAX

UNITS

NOTES

VCC for Retention Data

VDR

Data Retention Current

CE\ > (VCC-0.2V)

VIN > (VCC-0.2V)

or < 0.2V

ICCDR

1mA

Chip Deselect to Data

Retention Time

tCDR

0--

Operation Recovery Time

tRC

4, 11

12345678

123

1234

12345678

123

DATA RETENTION MODE

DR > 2V

4.5V

tCDR

CE\

Fig. 2

OUTPUT LOAD

EQUIVALENT

Fig. 1

OUTPUT LOAD

EQUIVALENT

+5V

255

30 pF

480

5 pF

+5V

255

480

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