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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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M24L28256SA Datenblatt(PDF) 4 Page - Elite Semiconductor Memory Technology Inc. |
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M24L28256SA Datenblatt(HTML) 4 Page - Elite Semiconductor Memory Technology Inc. |
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4 / 12 page  ESMT M24L28256SA Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2008 Revision : 1.1 4/12 AC Test Loads and Waveforms Parameters 3.0V (VCC) Unit R1 22000 Ω R2 22000 Ω RTH 11000 Ω VTH 1.50 V Switching Characteristics Over the Operating Range [8] -55 -70 Parameter Description Min. Max. Min. Max. Unit Read Cycle tRC Read Cycle Time 55[12] 70 ns tAA Address to Data Valid 55 70 ns tOHA Data Hold from Address Change 5 10 ns tACE CE LOW 55 70 ns tDOE OE LOW to Data Valid 25 35 ns tLZOE OE LOW to Low Z[9, 10] 5 5 ns tHZOE OE HIGH to High Z[9, 10] 25 25 ns tLZCE CE LOW 2 5 ns tHZCE CE HIGH 25 25 ns tSK[12] Address Skew 0 10 ns Write Cycle [11] tWC Write Cycle Time 55 70 ns tSCE CE LOW 45 55 ns tAW Address Set-Up to Write End 45 55 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-Up to Write Start 0 0 ns tPWE WE Pulse Width 40 55 ns tSD Data Set-Up to Write End 25 25 ns tHD Data Hold from Write End 0 0 ns tHZWE WE LOW to High-Z[9, 10] 25 25 ns tLZWE WE HIGH to Low-Z[9, 10] 5 5 ns Notes: 8. Test conditions assume signal transition time of 1V/ns or higher, timing reference levels of VCC(typ)/2, input pulse levels of 0V to VCC(typ), and output loading of the specified IOL/IOH and 30-pF load capacitance 9. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high-impedance state. 10. High-Z and Low-Z parameters are characterized and are not 100% tested. 11. The internal write time of the memory is defined by the overlap of WE , CE = VIL, . All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates write. 12. To achieve 55-ns performance, the read access should be CE controlled. In this case tACE is the critical parameter and tSK is satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable within 10 ns after the start of the read cycle. |
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