P89CV51RB2_09 datasheet(8/76 Pages) NXP

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P89CV51RB2_RC2_RD2_3

Product data sheet

Rev. 03 — 25 August 2009

8 of 76

NXP Semiconductors

P89CV51RB2/RC2/RD2

80C51 with 1 kB RAM, SPI

[1]

ALE loading issue: When ALE pin experiences higher loading (> 30 pF) during the reset, the microcontroller may accidentally enter into

modes other than normal working mode. The solution is to add a pull-up resistor from 3 k

Ω to 50 kΩ between e.g., ALE pin and V

DD.

[2]

For 6-clock mode, ALE is emitted at 1

⁄

3 of crystal frequency.

RST

Reset: While the oscillator is running, a HIGH logic state on this pin for two

machine cycles will reset the device.

External Access Enable: EA must be connected to VSS in order to enable

the device to fetch code from the external program memory. EA must be

strapped to VDD for internal program execution.

ALE

I/O

Address Latch Enable: ALE is the output signal for latching the low byte of

the address during an access to external memory. Normally the ALE[1] is

emitted at a constant rate of 1

⁄

6 the crystal frequency

[2] and can be used for

external timing and clocking. One ALE pulse is skipped during each access

to external data memory. However, if bit AO is set to 1, ALE is disabled.

XTAL1

Crystal 1: Input to the inverting oscillator ampliﬁer and input to the internal

clock generator circuits.

XTAL2

Crystal 2: Output from the inverting oscillator ampliﬁer.

VDD

supply

Power supply

VSS

supply

Ground

Table 3.

P89CV51RB2/RC2/RD2 Pin description …continued

Symbol

Type

Description

PLCC44

TQFP44

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