ADF4602 datasheet(21/36 Pages) AD

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ADF4602

Rev. 0 | Page 21 of 36

DC Offset Compensation

Due to the very high proportion of the total system gain assigned

to the analog baseband function, compensating for dc offsets is

an inherent part of any direct conversion solution. DC offsets

are characterized as falling into two categories: static or slow

varying and time varying

The ADF4602 architecture has been designed to reduce the

amount of time varying dc offsets. The device also includes a dc

offset control system. The control system consists of ADCs at

the baseband output to digitize dc offsets: a digital signal

processing block where the characteristics of the loop are

programmed for customization of the loops transfer function,

and trim DACs that are used to introduce the error term back

into the signal path. The offset control transfer function can

either be programmed to act as a servo loop that is automatically

triggered by a gain change or as a high-pass filter (HPF) with an

automatic fast settling mode that is also triggered by a gain

change. Parameters of the servo loop, high-pass filter, and fast

settling mode are set by the initial ADF4602 programming. In

operation, the dc offset control system is fully automatic and

does not require any external programming. Recommended

default programming conditions for the dc offset compensation

loop are shown in the Register Description section.

POWER MANAGEMENT

The ADF4602 contains integrated power management

requiring two external power supplies: 3.3 V VDD and 1.8 V

VINT. Figure 40 shows a block diagram.

VDD supplies the five integrated low drop-out regulators

(LDOs), VSUP1 to VSUP5, that are used to supply the vast

majority of the internal circuitry. VSUP6, VSUP7, and VSUP8

supply the receive PLL, transmit PLL, and reference block,

respectively. These nodes require external connections to

ensure good supply isolation and ensure a minimum level of

interference between the PLL/reference blocks and the rest of

the transceiver. VSUP6 and VSUP7 should be connected to

VSUP3, whereas VSUP8 should be connected to VSUP2.

Each node, VSUP1 to VSUP8, should be externally decoupled

to ground with a 0.1 μF capacitor. Y5V capacitors are not

recommended for use here. X7R, X5R, C0G, or a similar type of

capacitor should be used.

RX VCO

RX LNAs

TX VCO

1.8V

2.8V

1.9V

REF PATH

REF OP

(SER INT

READ)

TX MOD

TX BB

PWR DET

DACs

BASEBAND

AND

MIXERS

RX PLL

TX PLL

VSUP8

VSUP7

VSUP6

VSUP5

VSUP4

VSUP3

VSUP2

VSUP1

VBAT

VINT

ANALOG BB

OR VSUP2

DIGITAL 1.8V

SUPPLY

SERIAL

INTERFACE

LDO

Figure 40. Power Management Block

VINT supplies the serial interface enabling register data

preservation with minimum current consumption during

power-down. This should be supplied with 1.8 V externally.

The five LDOs are individually powered up/down via bits

ldoen[4:0] in Register 1. Table 7 summarizes the supply strategy.

Note that the reference path (VSUP8) supply is supplied from

an external source or the internal VSUP2. The external supply

option may be convenient so that the entire reference path can

be shut down by collapsing a single supply.

VSUP8 can also be programmed to supply the voltage used for

serial interface readback. See the Serial Port Interface (SPI)

section for more information.

Table 7. Power Management Strategy

Connection

Usage

Volts

VINT

External

Serial interface control

logic

1.8 V

VDD

External

Main device supply,

DAC1

3.3 V

VSUP1

Internal LDO1

Receive VCO

2.6 V

VSUP2

Internal LDO2

Receive baseband and

down-converter

2.8 V

VSUP3

Internal LDO3

Receive LNAs

1.9 V

VSUP4

Internal LDO4

Transmit VCO

2.6 V

VSUP5

Internal LDO5

Transmit baseband,

modulator, DAC2, and

GPOs

2.8 V

VSUP6

Connect to VSUP3

Receive synthesizer

1.9 V

VSUP7

Connect to VSUP3

Transmit synthesizer

1.9 V

VSUP8

VSUP2 or external

Reference path,

reference buffer outputs;

Optional: serial interface

readback

2.8 V

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