SNC15040

One Channel Speech Controller

Ver: 1.5

October 30, 2008

5

5.3 RAM

SNC15040 contains 64 nibble RAM (64 x 4-bits). The 64 nibble RAM is only one

page (page 0, 64 nibble RAM on each page). In our programming structure, users

can use the instructions, PAGE n (n=0) to switch and indicate the RAM page.

Besides, users can use direct mode, M0 ~ M63 in the data transfer type instructions,

to access all 64 nibbles of each page.

5.4 Power Down Mode

“End” instruction makes the IC entering into Stop Mode will stop the system clock for

power savings (<3uA @VDD=3V and <6uA @VDD=4.5V.) Any valid data transition

(L H or H L) occurring on any IO pin can be used to start the system clock and

return to normal operating mode.

5.5 Sampling Rate Counter

The unique sampling rate counter is designed in voice channel to be able to play

diverse voices at different sample playing rates. The playing rate can be adaptively set

up among from the wide ranges of 2.5KHz to 20KHz. This architecture yields a

high-quality voice synthesis that sounds very close to its original source when played

through the same amplifier and speaker circuitry.

5.6 I/O Ports

There are two 4-bit I/O ports P2 and P5. Any I/O can be individually programmed as

either input pull low or output. Any valid data transition (H L or L H) of P2 and P5

can reactivate the chip when it is in power-down stage.

I/O Port Configuration

Note:

(1) Weak N-MOS can serve as pull-low resistor.

(2) The driving/sink current of P2 & P5 is up to 8mA/16mA

Port Data

Port Status

To Internal Data Bus

Read Control

PAD

Weak