ATmega165-16AI datasheet(85/336 Pages) ATMEL

85 / 336 page

ATmega165/V

2573G–AVR–07/09

Figure 37 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode.

Figure 37. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with

Prescaler (f

clk_I/O/8)

8-bit Timer/Counter

Timer/Counter Control

• Bit 7 – FOC0A: Force Output Compare A

The FOC0A bit is only active when the WGM00 bit specifies a non-PWM mode. How-

ever, for ensuring compatibility with future devices, this bit must be set to zero when

TCCR0 is written when operating in PWM mode. When writing a logical one to the

FOC0A bit, an immediate compare match is forced on the Waveform Generation unit.

The OC0A output is changed according to its COM0A1:0 bits setting. Note that the

FOC0A bit is implemented as a strobe. Therefore it is the value present in the

COM0A1:0 bits that determines the effect of the forced compare.

A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode

using OCR0A as TOP.

The FOC0A bit is always read as zero.

• Bit 6, 3 – WGM01:0: Waveform Generation Mode

These bits control the counting sequence of the counter, the source for the maximum

(TOP) counter value, and what type of waveform generation to be used. Modes of oper-

ation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare

match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See Table

42 and “Modes of Operation” on page 80.

OCFnx

OCRnx

TCNTn

(CTC)

TOP

TOP - 1

TOP

BOTTOM

BOTTOM + 1

clk

I/O

clk

(clk

I/O/8)

Bit

FOC0A

WGM00

COM0A1

COM0A0

WGM01

CS02

CS01

CS00

TCCR0

Read/Write

R/W

Initial Value

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