AT25DF041A-MH-T datasheet(13/41 Pages) ATMEL

13 / 41 page

3668D–DFLASH–9/08

AT25DF041A

If the address specified by A23 - A0 points to a memory location within a sector that is in the pro-

tected state, then the Block Erase command will not be executed, and the device will return to

the idle state once the CS pin has been deasserted. In addition, with the larger Block Erase

sizes of 32K and 64 Kbytes, more than one physical sector may be erased (e.g. sectors 18

through 15) at one time. Therefore, in order to erase a larger block that may span more than one

sector, all of the sectors in the span must be in the unprotected state. If one of the physical sec-

tors within the span is in the protected state, then the device will ignore the Block Erase

command and will return to the idle state once the CS pin is deasserted.

The WEL bit in the Status Register will be reset back to the logical “0” state if the erase cycle

aborts due to an incomplete address being sent or because a memory location within the region

to be erased is protected.

While the device is executing a successful erase cycle, the Status Register can be read and will

indicate that the device is busy. For faster throughput, it is recommended that the Status Regis-

ter be polled rather than waiting the t

BLKE time to determine if the device has finished erasing. At

some point before the erase cycle completes, the WEL bit in the Status Register will be reset

back to the logical “0” state.

The device also incorporates an intelligent erase algorithm that can detect when a byte location

fails to erase properly. If an erase error occurs, it will be indicated by the EPE bit in the Status

Figure 8-5.

Block Erase

SCK

MSB

CCCCCCCC

410 11

812

29 30

27 28

OPCODE

AAAA

AAA

ADDRESS BITS A23-A0

HIGH-IMPEDANCE

AT25DF041A-MH-T Datenblatt(PDF) 13 Page - ATMEL Corporation