MAXQ3181-RAN+ datasheet(33/84 Pages) MAXIM

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Low-Power, Active Energy, Polyphase AFE

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CFP Pulse Width (PLS1_WD) (0x020)

This register designates the width of the CFP pulse, that is, the duration of the period that the CFP pulse is in the

active state. This value is given in ADC frame times (about 320μs). The default value of 0x9C (156 decimal) provides

a pulse width of about 50ms.

Bit:

Name:

CFP Pulse-Width High Byte

Reset:

0x00

Bit:

Name:

CFP Pulse-Width Low Byte

Reset:

0x9C

Meter Pulse Configuration

Pulse Configuration—CFP Output (PLSCFG1) (0x01E)

This register selects which phases are included in the CFP pulse output and also selects which quantity is accumu-

lated to drive the pulse output.

Bit:

Name:

QNSEL

PHASEC

PHASEB

PHASEA

Reset:

0x0

BIT

NAME

FUNCTION

7:3

QNSEL

CFP Pulse Output Source Select. This five-bit field determines what meter value will be accumulated in

each of the phases to produce the CFP pulse output. All other values are reserved.

00000 = Net real energy

00001 = Absolute real energy

00100 = Apparent energy

00110 = IRMS

00111 = VRMS

01000 = Real energy delivered to load

01001 = Real energy delivered to line

PHASEC

CFP Phase C Inclusion. When this bit is set, phase C is included in CFP pulse generation.

PHASEB

CFP Phase B Inclusion. When this bit is set, phase B is included in CFP pulse generation.

PHASEA

CFP Phase A Inclusion. When this bit is set, phase A is included in CFP pulse generation.

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