MPC8536BVTATH datasheet(35/128 Pages) FREESCALE

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DDR2 and DDR3 SDRAM

MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

2.6.2.2

DDR2 and DDR3 SDRAM Interface Output AC Timing Specifications

Table 19 contains the output AC timing targets for the DDR2 and DDR3 SDRAM interface.

Table 19. DDR SDRAM Output AC Timing Specifications

At recommended operating conditions with GVDD of 1.8 V ± 5% for DDR2 or 1.5 V ± 5% for DDR3.

Parameter

Symbol 1

Min

Max

Unit

Notes

MCK[n] cycle time, MCK[n]/MCK[n] crossing

tMCK

3.0

ADDR/CMD output setup with respect to MCK

tDDKHAS

667 MHz

1.10

—

533 MHz

1.48

—

400 MHz

1.95

—

ADDR/CMD output hold with respect to MCK

tDDKHAX

667 MHz

1.10

—

533 MHz

1.48

—

400 MHz

1.95

—

MCS[n] output setup with respect to MCK

tDDKHCS

667 MHz

1.10

—

533 MHz

1.48

—

400 MHz

1.95

—

MCS[n] output hold with respect to MCK

tDDKHCX

667 MHz

1.10

—

533 MHz

1.48

—

400 MHz

1.95

—

MCK to MDQS Skew

tDDKHMH

<= 667 MHz

–0.6

0.6

MDQ/MECC/MDM output setup with respect to

MDQS

tDDKHDS,

tDDKLDS

667 MHz

450

—

533 MHz

538

—

400 MHz

700

—

MDQ/MECC/MDM output hold with respect to

MDQS

tDDKHDX,

tDDKLDX

667 MHz

450

—

533 MHz

538

—

400 MHz

700

—

MDQS preamble start

tDDKHMP

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