2

Order Information

Figure 2. HSDL-7002 Pin Configuration

Part Number Packaging Type

Quantity

HSDL-7002

Tape and Reel

2500

I/O Pins Configuration Table

Marking Information

The unit is marked with A7002 and ‘yyww’ on the chip.

yy = year

ww = work week

Note:

There are two methods of putting the internal oscillator cell in POWERDOWN MODE. Whenever the CLK_SEL pin is asserted high (external clock

select) the oscillator is automatically put in powerdown mode, or whenever the POWERDN pin asserted high.

Name

Type

Function

1

TXD

Digital In

Negative edge triggered input signal that is normally tied to the SOUT signal

of the UART (serial data to be transmitted). Data is modulated and output as

IR_TXD.

2

RXD

Digital Out

Output signal normally tied to SIN signal of a UART (received serial data).

RXD is the demodulated output of IR_RXD.

3

A0

Digital In

Clock Multiplex Signal

4

A1

Digital In

Clock Multiplex Signal

5

A2

Digital In

Clock Multiplex Signal

6

CLK_SEL

Digital In

Used to activate either the internal or external clock. A high on this line

activated the external clock (16XCLK) and a low activates the internal clock.

When the external clock is activated, the internal oscillator is put in POWERDN

mode.

7

GND

Chip Ground

8

NRST

Digital In

chine. This signal can be tied to POR (Power-On-Reset) or Vcc.

9

IR_RXD

Digital In

Input from SIR optoelectronics. Input signal is a 3/16th or 1.63 ms pulse that is

demodulated to generate RXD output signal.

10 IR_TXD

Digital Out

This is the modulated TXD signal.

11 PULSEMOD Digital In

(with pull down)

A high level on this input put the chip into the monoshot transmit mode. In

this mode, when there is a negative transition on the TXD input, a rising edge

on the internal transmit modulation state machine will activate a high pulse

on IR_TXD for 6 crystal clock cycles. With a 3.6864 MHz crystal, this corre-

sponds to 1.63 ms. This mode cannot be used in conjunction with the 16XCLK

clock. It is meant to be used with the external crystal clock. By default, this

input pin is pulled to GND

12 POWERDN Digital In

(with pull down)

A high on this input put only the internal oscillator cell in POWERDN mode.

The cell is normally not powered down.

13 OSCOUT

Analog Out

Oscillator Output

14 OSCIN

Analog In

Oscillator Input

15 Vcc

Power

16 16XCLK

Digital In

Positive edge triggered input clock that is set to 16 times the data transmis-

sion baud rate. The encode and decode schemes require this signal. The signal

is usually tied to a UART’s BAUDOUT signal. The 16XCLK may be provided by

application circuitry if BAUDOUT is not available. This signal is required when

the internal clock is not used.

PIN #1

CORNER

Pin 12

Pin 11

Pin 10

Pin 9

Pin 4

Pin 3

Pin 2

Pin 1