TS8GDOM40V datasheet(49/52 Pages) TRANSCEND

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Transcend Information Inc.

Ver 1.7

Host Terminating an Ultra DMA Data-Out Burst

Termination of an Ultra DMA Data-Out burst by the host is shown in below: Ultra DMA Data-Out

Burst Host Termination Timing while timing parameters are specified in Page 12: Ultra DMA Data Burst

Timing Requirements and timing parameters are described in Page 13: Ultra DMA Data Burst Timing

Descriptions.

The following steps shall occur in the order they are listed unless otherwise specifically allowed:

(a) The host shall initiate termination of an Ultra DMA data burst by not generating HSTROBE edges.

(b) The host shall assert STOP no sooner than tSS after it last generated an HSTROBE edge.The host

shall not negate STOP again until after the Ultra DMA data burst is terminated.

DMARQ again until after the Ultra DMA data burst is terminated.

(d) The device shall negate -DDMARDY within tLI after the host has negated STOP. The device shall not

assert -DDMARDY again until after the Ultra DMA data burst termination is complete.

(e) If HSTROBE is negated, the host shall assert HSTROBE within tLI after the device has negated

DMARQ. No data shall be transferred during this assertion. The device shall ignore this transition on

HSTROBE. HSTROBE shall remain asserted until the Ultra DMA data burst is terminated.

(f) The host shall place the result of its CRC calculation on D[15:00] (see ATA specification Ultra DMA

CRC Calculation).

(g) The host shall negate -DMACK no sooner than tMLI after the host has asserted HSTROBE and STOP

and the device has negated DMARQ and -DDMARDY, and no sooner than tDVS after placing the result

of its CRC calculation on D[15:00].

(h) The device shall latch the host’s CRC data from D[15:00] on the negating edge of -DMACK.

(i) The device shall compare the CRC data received from the host with the results of its own CRC

calculation. If a miscompare error occurs during one or more Ultra DMA data bursts for any one

command, at the end of the command, the device shall report the first error that occurred (see ATA

specification Ultra DMA CRC Calculation).

(j) While operating in True IDE mode, the device shall release -DDMARDY within tIORDYZ after the host

has negated -DMACK.

(k) The host shall neither negate STOP nor negate HSTROBE until at least tACK after negating -DMACK.

(l) In True IDE mode, the host shall not assert -IOWR, -CS0, -CS1, nor A[02:00] until at least tACK after

negating DMACK..

TS8GDOM40V Datenblatt(PDF) 49 Page - Transcend Information. Inc.

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