TS2GDOM40V-S datasheet(7/34 Pages) TRANSCEND

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d 4

0---P

Piiin

n IIID

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h M

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M ~

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Transcend Information Inc.

Ver 1.2

True IDE PIO Mode Timing Diagram

Figure 1: True IDE PIO Mode Timing Diagram

Notes:

(1) Device address consists of -CS0, -CS1, and A[02::00]

(2) Data consists of D[15::00] (16-bit) or D[07::00] (8 bit)

(3) -IOCS16 is shown for PIO modes 0, 1 and 2. For other modes, this signal is ignored.

(4) The negation of IORDY by the device is used to extend the PIO cycle. The determination of whether the cycle is

to be extended is made by the host after tA from the assertion of -IORD or -IOWR. The assertion and negation

of IORDY is described in the following three cases:

(4-1) Device never negates IORDY: No wait is generated.

(4-2) Device starts to drive IORDY low before tA, but causes IORDY to be asserted before tA: No wait

generated.

(4-3) Device drives IORDY low before tA: wait generated. The cycle completes after IORDY is reasserted. For

cycles where a wait is generated and -IORD is asserted, the device shall place read data on D15-D00 for

tRD before causing IORDY to be asserted.

TS2GDOM40V-S Datenblatt(PDF) 7 Page - Transcend Information. Inc.