WM0834LIN datasheet(10/16 Pages) WOLFSON

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Wolfson Microelectronics

WM0834, WM0838

Functional Description

Multiplexer Operation and Addressing

WM0834 and WM0838 use an input multiplexer scheme

thet provides multiple analogue channels, configurable for

single-ended or differential operation and also for WM0838,

a pseudo-differential mode that will perform an analogue to

digital (A/D) conversion of the voltage difference between

any analogue input and a common terminal (COM).

WM0834/8 uses a successive approximation routine to

perform A/D conversion that employs a sample data

comparator structure which always performs conversion on

a differential voltage. Conversion takes place on the

voltage difference between assigned "+" and "-" inputs and

the converter expects the "+" input to be the most positive. If

the "+" input is more negative than "-" then the converter

gives an all zeros output.

Assignment of inputs is made for a single-ended signal

between an "+" input and analogue ground (AGND) or COM

for WM0838, or for differential inputs between adjacent pairs

of inputs of either polarity.

The COM input of WM0838 acts as the "-" input for pseudo-

differential "+" inputs and can be an arbitrary voltage such

as an analogue common not at ground potential in single

supply applications.

Prior to the start of every conversion the input configuration

is assigned during the MUX addressing sequence achieved

by serially shifting data into the Data Input (DI) on the rising

edges of the clock input.

The MUX address selects which analogue inputs are

enabled, either single-ended, differential or pseudo-

differential (WM0838). For differential inputs the polarity of

the selected pairs of adjacent inputs are also assigned.

Differential inputs can only be assigned to adjacent channel

pairs.

The MUX addressing tables give full details of input

assignments.

Initiating Conversion and the Digital Interface

WM0834 and WM0838 are controlled from a processor via

a serial interface comprising Data In (DI) and Data Out (DO),

Chip Select (CS) and Clock (CLK) inputs and a SAR

Status (SARS) output.

A conversion is initiated by pulling the chip select (CS) line

low. CS must be kept low for an entire conversion.

The start bit and the MUX assignment bits on DI are

clocked in on the rising edges of the clock input, which

may be generated by the processor or run continuously.

WM0834 uses three MUX assignment bits and WM0838

uses four.

When the logic "1" start bit is clocked into the start

conversion location of the multiplexer input register, the

analogue MUX inputs are selected. After 1/2 a clock

period delay to allow for the selected MUX output to

settle, the conversion commences using the successive

approximation technique. At this time, the SARS output

goes high to indicate a conversion is in progress and the

DI input is disabled.

When conversion begins, the A/D conversion result from

the output of the SARS comparator appears at the DO

output on each falling edge of the clock (see Functional

Timing Diagrams).

With the successive approximation A/D conversion

routine, the analogue input is compared with the output of

a digital to analogue converter (DAC) for each bit by the

SARS comparator and a decision made on whether the

analogue input is higher or lower than the DAC output.

Successive bits, MSB to LSB are input to the DAC and

remain in its input if the analogue comparison decides the

analogue input is higher than the DAC output. If not, the

bit is removed from the DAC input. The output from the

SARS comparator forms the resulting input to the DAC

and the A/D conversion output, and is read by the

processor as conversion takes place in MSB to LSB

order. After 8 clock periods, the conversion is complete

and this is indicated by SARS being brought low a 1/2

clock period later.

All bits of the conversion are stored in an output shift

data has been output.

For WM0838, the commencement of output data in a LSB

first format can be controlled by use of the SE input. If

the SE input is held high, the LSB output will remain on

the DO output. When SE is brought low, LSB first data

output will begin on DO. After 8-bits of LSB first data have

been output, the DO output goes low and remains low

until CS is brought high, when outputs (DO & SARS) go

into a high impedance state.

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