WM9704Q

Production Data

WOLFSON MICROELECTRONICS LTD

PD Rev 2.3 January 2001

14

The filtered difference signal is gain adjusted by an amount set using the 4-bit value written to

register 22h bits 3 to 0. Value 0h is disable, value Fh is maximum effect. Typically a value of 8h is

optimum. The user interface would most typically use a slider type of control to allow the user to

adjust the level of enhancement to suit the program material. Bit D13 3D in register 20h is the overall

3D enable bit. The capability register 00h reads back the value 11000 in bits D14 to D10. This

corresponds to decimal 24, which is registered with Intel as Wolfson Stereo Enhancement.

Note that the external capacitors setting the filtering poles applied to the difference signal may be

adjusted in value, or even replaced with a direct connection between the pins. If such adjustments

are made, then the amount of difference signal fed back into the main signal paths may be

significant, and can cause large signals which may limit, distort, or overdrive signal paths or

speakers. Adjust these values with care, to select the preferred acoustic effect.

There is no provision for pseudo-stereo effects. Mono signals will have no enhancement applied

(if the signals are in phase and of the same amplitude).

Signals from the PCM DAC channels do not have stereo enhancement applied. It is assumed that

these signals will already have been processed digitally with any required 3D-enhancement effect.

Applying the analogue 3D enhancement will corrupt this digital effect. This is equivalent to setting the

POP bit in register 20h. As a result, the readback value of this bit is fixed as 1, and attempts to

change it will be ignored. POP bit is set to one and cannot be re-set.

VARIABLE SAMPLE RATE SUPPORT

The DACs and ADCs on this device support all the recommended sample rates specified in the Intel

Revision 2.1 specification for both audio and modem rates. Default rates are 48ks/s. If alternative

rates are selected, the AC’97 interface continues to run at 48k words per second, but data is

transferred across the link in bursts such that the net sample rate selected is achieved. It is up to the

AC’97 Revision 2.1 compliant controller to ensure that data is supplied to the AC link, and received

from the AC link, at the appropriate rate.

The device supports on demand sampling. That is, when the DAC signal processing circuits need

another sample, a sample request is sent to the controller which must respond with a data sample in

the next frame it sends. For example, if a rate of 24ks/s is selected, on average the device will

request a sample from the controller every other frame, for each of the stereo DACs. Note that if an

unsupported rate is written to one of the rate registers, the rate will default to the nearest rate

supported. The register will then respond when interrogated with the supported rate the device has

defaulted to.

ADCs are controlled similarly but with one difference: Normally the left and right channel ADCs

sample at the same rate.

AUDIO

SAMPLE RATE

CONTROL VALUE

D15 TO D0

MODEM

SAMPLE RATE

CONTROL VALUE

D15 TO D0

7200

1C20

8228.57 (57600/7)

2024

8000

1F40

8400

20D0

11025

2B11

9000

2328

16000

3E80

9600

2580

22050

5622

10285.71 (72000/7)

282D

44100

AC44

12000

2EE0

48000

BB80

13714.28 (96000/7)

3592

19200

4B00

24000

5DC0

Table 3 Variable Sample Rates Supported