Technical Note

BU4015B,BU4015BF,BU4021B,BU4021BF,

BU4094BC,BU4094BCF,BU4094BCFV,BU4538B,BU4028B

13/17

www.rohm.com

2009.06 - Rev.A

© 2009 ROHM Co., Ltd. All rights reserved.

1

2

4

5

6

7

14

13

12

9

P8

P5

DS

CLOCK

P/S

Q7

11

3

10

P6

Q6

Q8

P4

P3

P2

P1

8

VSS

15

P7

16

VDD

P8

Q6

Q8

P4

P3

P2

P1

P7

P6

Q5

Q7

DS

CLOCK

P/S

●

Description of BU4021B series model

Function: 8-stage static shift register

1) Description of operation

BU4021B is an 8-bit static shift register capable of parallel input/series output and series input/series output. In parallel

operation, DS (data) being asynchronous with the clock is inputted into each F/F and obtained at output.

In series operation, DS (data) is triggered by clock.

When P/S input level is “H”, parallel operation is effective, and when P/S input level is “L”, series operation is effective.

PIN arrangement

Block diagram

Truth table

●

Description of BU4094BC series model

Function: Dual 4-bit static shift register

1) Description of operation

BU4094BC is an 8-stage shift/store register provided in each stage with a data latch with 3-state output. Data read into

shift register is read into the latch during the fall time of asynchronous STROBE input, and in the data transfer mode,

output can be held. Data is passed through the latch and outputted when the STROBE is in “H” level. Because the parallel

output becomes high impedance when the OUTPUT ENABLE terminal is set to “L” level by 3-state, the parallel output can

be connected directly with the 8-bit pass line.

PIN arrangement

PIN description

PIN No.

Symbol

I/O

Function

1

P8

I

Parallel data input 8

2

Q6

O

Output 6

3

Q8

O

Output 8

4

P4

I

Parallel data input 4

5

P3

I

Parallel data input 3

6

P2

I

Parallel data input 2

7

P1

I

Parallel data input 1

8

VSS

―

Power supply(-)

9

P/S

I

Parallel/Serial

10

CLOCK

I

Clock input

11

DS

I

Serial data input

12

Q7

O

Output 7

13

P5

I

Parallel data input 5

14

P6

I

Parallel data input 6

15

P7

I

Parallel data input 7

16

VDD

―

Power supply (+)

PIN description

PIN No.

Symbol

I/O

Function

1

STROBE

I

Latch input

2

SERIALIN

I

Data input

3

CLOCK

I

Clock input

4

Q1

O

Parallel data input Q1

5

Q2

O

Parallel data input Q2

6

Q3

O

Parallel data input Q3

7

Q4

O

Parallel data input Q4

8

VSS

―

Power supply(-)

9

QS

O

Serial data output QS

10

Q’S

O

Serial data output Q’S

11

Q8

O

Parallel data output Q8

12

Q7

O

Parallel data output Q7

13

Q6

O

Parallel data output Q6

14

Q5

O

Parallel data output Q5

15

ENABLE

I

Output enable

16

VDD

―

Power supply (+)

CLOCK

D

RESET

Q0

Q1

Q2

Q3

X

X

H

L

LLL

No Change

X

H

LL

L

L

LQ0

H

Q1

Q2

Q0

Q1

Q2

CLOCK

DS

P/S

Dm

Qm*

X

XH

L

H

L

HH

X：Don't Care

*：Q6,Q7,Q8は外部

X：Don't Care

1

2

4

5

6

7

14

13

12

9

STROBE

Q6

Q8

Q'S

QS

Q7

11

3

10

Q5

SERIAL

CLOCK

Q1

Q2

Q3

Q4

8

VSS

16

VDD

IN

ENABLE

STROBE

SERIA

IN

CLOCK

Q1

Q2

Q3

Q4

Q6

Q8

Q'S

QS

Q7

Q5

OUTPUT

ENABLE

CLOCK

D

D

C

Q

D

C

Q

D

C

Q

D

C

Q

D

C

Q

D

C

D

C

Q

Q

D

CQ

Q

Q

Q

P/S

Q

Q

P1

P2

P3

P4

P5

P6

P7

P8

*:Q6,Q7,Q8:

outside