74ABT652A_2

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Product data sheet

Rev. 02 — 12 March 2010

6 of 19

NXP Semiconductors

74ABT652A

Octal transceiver/register; non-inverting; 3-state

6.

Functional description

6.1 Function table

[1]

H = HIGH voltage level;

L = LOW voltage level;

X = don’t care;

↑ = LOW-to-HIGH clock transition.

[2]

The data output function may be enabled or disabled by various signals at the OEBA and OEAB inputs. Data input functions are always

enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the clock.

[3]

If both select controls (SAB and SBA) are LOW, then clocks can occur simultaneously. If either select control is HIGH, the clocks must

be staggered in order to load both registers.

Figure 3 demonstrates the four fundamental bus-management functions that can be

performed with the 74ABT652A.

The select pins determine whether data is stored or transferred through the device in real

time.

The output enable pins determine the direction of the data flow.

Table 3.

Function table [1]

Inputs

Data I/O

Operating mode

OEAB

OEBA

CPAB

CPBA

SAB

SBA

An

Bn

L

H

H or L

H or L

X

X

input

input

isolation

LH

↑↑

X

X

input

input

store A and B data

XH

↑

H or L

X

X

input

unspecified

output [2]

store A, hold B

HH

↑↑

[3]

X

input

unspecified

output [2]

store A in both registers

L

X

H or L

↑

X

X

unspecified

output [2]

input

hold A, store B

LL

↑↑

X

[3]

unspecified

output [2]

input

store B in both registers

L

L

X

X

X

L

output

input

real time B data to A bus

L

L

X

H or L

X

H

output

input

stored B data to A bus

H

H

X

X

L

X

input

output

real time A data to B bus

H

H

H or L

X

H

X

input

output

store A data to B bus

H

L

H or L

H or L

H

H

output

output

stored A data to B bus;

stored B data to A bus