TMX320C6720RFP300 datasheet(49/118 Pages) TI

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4.11.3 EMIF Electrical Data/Timing

TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720

Floating-Point Digital Signal Processors

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SPRS370E – SEPTEMBER 2006 – REVISED JULY 2008

Table 4-5 through Table 4-10 assume testing over recommended operating conditions (see Figure 4-7

through Figure 4-13).

Table 4-5. 100-MHz EMIF SDRAM Interface Timing Requirements(1)

NO.

MIN

MAX UNIT

tsu(EM_DV-EM_CLKH)

Input setup time, read data valid on D[31:0] before EM_CLK rising

th(EM_CLKH-EM_DIV)

Input hold time, read data valid on D[31:0] after EM_CLK rising

1.9

(1)

For more information about supported EMIF frequency, see Table 2-1.

Table 4-6. 100-MHz EMIF SDRAM Interface Switching Characteristics(1)

NO.

PARAMETER

MIN

MAX UNIT

tc(EM_CLK)

Cycle time, EMIF clock EM_CLK

tw(EM_CLK)

Pulse width, EMIF clock EM_CLK high or low

td(EM_CLKH-EM_CSV)S

Delay time, EM_CLK rising to EM_CS[0] valid

7.7

toh(EM_CLKH-EM_CSIV)S

Output hold time, EM_CLK rising to EM_CS[0] invalid

1.15

td(EM_CLKH-EM_WE-DQMV)S

Delay time, EM_CLK rising to EM_WE_DQM[3:0] valid

7.7

toh(EM_CLKH-EM_WE-DQMIV)S

Output hold time, EM_CLK rising to EM_WE_DQM[3:0] invalid

1.15

td(EM_CLKH-EM_AV)S

Delay time, EM_CLK rising to EM_A[12:0] and EM_BA[1:0] valid

7.7

Output hold time, EM_CLK rising to EM_A[12:0] and EM_BA[1:0]

toh(EM_CLKH-EM_AIV)S

1.15

invalid

td(EM_CLKH-EM_DV)S

Delay time, EM_CLK rising to EM_D[31:0] valid

7.7

toh(EM_CLKH-EM_DIV)S

Output hold time, EM_CLK rising to EM_D[31:0] invalid

1.15

td(EM_CLKH-EM_RASV)S

Delay time, EM_CLK rising to EM_RAS valid

7.7

toh(EM_CLKH-EM_RASIV)S

Output hold time, EM_CLK rising to EM_RAS invalid

1.15

td(EM_CLKH-EM_CASV)S

Delay time, EM_CLK rising to EM_CAS valid

7.7

toh(EM_CLKH-EM_CASIV)S

Output hold time, EM_CLK rising to EM_CAS invalid

1.15

td(EM_CLKH-EM_WEV)S

Delay time, EM_CLK rising to EM_WE valid

7.7

toh(EM_CLKH-EM_WEIV)S

Output hold time, EM_CLK rising to EM_WE invalid

1.15

tdis(EM_CLKH-EM_DHZ)S

Delay time, EM_CLK rising to EM_D[31:0] 3-stated

7.7

tena(EM_CLKH-EM_DLZ)S

Output hold time, EM_CLK rising to EM_D[31:0] driving

1.15

(1)

For more information about supported EMIF frequency, see Table 2-1.

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