74LVC2G08GD datasheet(1/16 Pages) NXP

1 / 16 page

1.

General description

The 74LVC2G08 provides a 2-input AND gate function.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of the

74LVC2G08 as a translator in a mixed 3.3 V and 5 V environment.

This device is fully speciﬁed for partial power-down applications using IOFF. The IOFF

circuitry disables the output, preventing a damaging backﬂow current through the device

when it is powered down.

2.

Features

I Wide supply voltage range from 1.65 V to 5.5 V

I 5 V tolerant outputs for interfacing with 5 V logic

I High noise immunity

I ±24 mA output drive (VCC = 3.0 V)

I CMOS low power consumption

I Complies with JEDEC standard:

N JESD8-7 (1.65 V to 1.95 V)

N JESD8-5 (2.3 V to 2.7 V)

N JESD8-B/JESD36 (2.7 V to 3.6 V)

I Latch-up performance exceeds 250 mA

I Direct interface with TTL levels

I Inputs accept voltages up to 5 V

I ESD protection:

N HBM JESD22-A114E exceeds 2000 V

N MM JESD22-A115-A exceeds 200 V

I Multiple package options

I Speciﬁed from −40 °C to +85 °C and −40 °C to +125 °C

74LVC2G08

Dual 2-input AND gate

Rev. 08 — 9 June 2008

Product data sheet

Ähnliche Beschreibung - 74LVC2G08GD

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