74LVC2G240DP datasheet(2/16 Pages) NXP

2 / 16 page

74LVC2G240_4

Product data sheet

Rev. 04 — 29 February 2008

2 of 16

NXP Semiconductors

74LVC2G240

Dual inverting buffer/line driver; 3-state

Ordering information

Marking

Functional diagram

Table 1.

Ordering information

Type number

Package

Temperature range

Name

Description

Version

74LVC2G240DP

−40 °C to +125 °C

TSSOP8

plastic thin shrink small outline package; 8 leads;

body width 3 mm; lead length 0.5 mm

SOT505-2

74LVC2G240DC

−40 °C to +125 °C

VSSOP8

plastic very thin shrink small outline package; 8 leads;

body width 2.3 mm

SOT765-1

74LVC2G240GT

−40 °C to +125 °C

XSON8

plastic extremely thin small outline package; no leads;

8 terminals; body 1

× 1.95 × 0.5 mm

SOT833-1

74LVC2G240GM

−40 °C to +125 °C

XQFN8U

plastic extremely thin quad ﬂat package; no leads;

8 terminals; UTLP based; body 1.6

× 1.6 × 0.5 mm

SOT902-1

Table 2.

Marking codes

Type number

Marking code

74LVC2G240DP

V240

74LVC2G240DC

V40

74LVC2G240GT

V40

74LVC2G240GM

V40

Fig 1.

Logic symbol

Fig 2.

IEC logic symbol

001aah782

1OE

2OE

001aah783

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