LTC2757

13

2757f

1. Load ±5V range with the output at 0V. Note that since span and code are updated together, the output, if started at

0V, will stay there. The 18-bit DAC code is shown in hex for compactness.

OPERATION

WR

2757 TD03

SPAN I/O

INPUT

DATA I/O

INPUT

UPD

D/S

010

READ = LOW

UPDATE

offset or bipolar zero error. The offset change expressed

in LSB is the same for any output range:

ΔV

• 2048

–2048 LSB in any output range, assuming a 5V reference

In voltage terms, the offset delta is attenuated by a factor

of 32, 64 or 128, depending on the output range. (These

functions hold regardless of reference voltage.)

[0V to 5V, ±2.5V spans]

[0V to 10V, ±5V, –2.5V to

7.5V spans]

[±10V span]

error or to compensate for reference errors. The gain er-

ror change expressed in LSB is the same for any output

range:

ΔGE =

• 2048

The gain-error delta is non-inverting for positive reference

voltages.

Note that this pin compensates the gain by altering the

inverted reference voltage V(REF). In voltage terms,

the V(REF) delta is inverted and attenuated by a factor

of 128.

The nominal input range of these pins is ±5V; other volt-

ages of up to ±15V may be used if needed. However, do

not use voltages divided down from power supplies; ref-

erence-quality, low-noise inputs are required to maintain

the best DAC performance.

pin should be driven with a Thevenin-equivalent impedance

of 10k or less to preserve the settling performance of the

LTC2757. It should be shorted to GND if not used.

is intended for use with fixed reference voltages only. It

should be shorted to GND if not used.

OPERATION—EXAMPLES