ADS5400IPZP datasheet(33/48 Pages) TI

33 / 48 page

ADS5400

AVDD5

Internal

Clock

Buffer

GND

AVDD5

~5.25nHBondWire

~0.35pF

Package

~0.2pF

Bondpad

~0.35pF

Package

~0.2pF

Bondpad

400 W

AVDD5V/2

200 W

CLKINN

400 W

10 W

0.25pF

10 W

CLKINP

CLK

ADS5400

CLK

SquareWaveor

SineWave

0.01 F

ADS5400

www.ti.com

SLAS611B – OCT 2009 – REVISED MARCH 2010

Clock Inputs

The ADS5400 clock input can be driven with either a differential clock signal or a single-ended clock input. The

equivalent clock input circuit can be seen in Figure 30. In low-input-frequency applications, where jitter may not

be a big concern, the use of a single-ended clock (as shown in Figure 31) could save cost and board space

without much performance tradeoff. When clocked with this configuration, it is best to connect CLK to ground

with a 0.01-mF capacitor, while CLK is ac-coupled with a 0.01-mF capacitor to the clock source, as shown in

Figure 31.

Figure 30. Clock Input Circuit

Figure 31. Single-Ended Clock

Product Folder Link(s): ADS5400

ADS5400IPZP Datenblatt(PDF) 33 Page - Texas Instruments

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