L99PD08 datasheet(35/41 Pages) STMICROELECTRONICS

35 / 41 page

L99PD08

SPI

Doc ID 15872 Rev 3

35/41

Note:

If a digital device and no detailed diagnosis is selected, also ambiguous failures are

reflected in this register (channel is turned off if ASDT is selected).

Note:

In digital mode, the OL failure can not be cleared in off-state when detailed diagnosis is

disabled. To clear the OL bit, the detailed diagnosis has to be enabled or the failure has to

be removed and cleared in on-state.

If a digital device and no detailed diagnosis is selected, also ambiguous failures are

reflected in this register.

Table 41.

AUX_STATUS Registers, hex2F (RC-Type)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CS_time50% CS_timeout

CLK_IN1

Warm

CLK_IN0

Warm

CLK_IN0 Warn, CLK_IN1 Warn: the corresponding warn bit is set when the input frequency

is below 5kHz (fPWMmin_set = 19 Hz) and reset when the frequency is above 7 kHz

fPWMmin_reset = 28 Hz. The hysteresis was implemented not to get a flickering on the PWM

output. If the warn bit is set the PWM is generated by an internally generated signal

(f = 122 Hz). The warn bit does not set the global error flag.

CLK_INx Warn 0

input clock frequency fCLK_INx > 7 kHz.

input clock frequency fCLK_INx < 5 kHz (fPWMmin < 19 Hz). The internal

generated PWM clock signal is used.

CS_timeout

this bit is set when a CS-timeout occurred. It has to be cleared by a clear

command (Op code b10)

CS_time50%

this bit is set when 50% of the CS-timeout time is reached.

Table 42.

OT_FAULT Registers, hex30 (RC-Type)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CH7

CH6

CH5

CH4

CH3

CH2

CH1

CH0

CHx

0 on channel CHx wasn’t detected dedicated failure

1 on channel CHx was detected dedicated failure

Table 43.

OL_FAULT Registers, hex31 (RC-Type)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CH7

CH6

CH5

CH4

CH3

CH2

CH1

CH0

CHx

0 on channel CHx wasn’t detected dedicated failure

1 on channel CHx was detected dedicated failure

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