P89LPC9331FDH datasheet(49/93 Pages) NXP

49 / 93 page

P89LPC9331_9341_9351_9361_3

Product data sheet

Rev. 03 — 2 June 2009

49 of 93

NXP Semiconductors

P89LPC9331/9341/9351/9361

8-bit microcontroller with accelerated two-clock 80C51 core

7.25 SPI

The P89LPC9331/9341/9351/9361 provides another high-speed serial communication

interface: the SPI interface. SPI is a full-duplex, high-speed, synchronous communication

bus with two operation modes: Master mode and Slave mode. Up to 3 Mbit/s can be

supported in either Master mode or Slave mode. It has a Transfer Completion Flag and

Write Collision Flag Protection.

The SPI interface has four pins: SPICLK, MOSI, MISO and SS:

• SPICLK, MOSI and MISO are typically tied together between two or more SPI

devices. Data ﬂows from master to slave on MOSI (Master Out Slave In) pin and ﬂows

from slave to master on MISO (Master In Slave Out) pin. The SPICLK signal is output

in the Master mode and is input in the Slave mode. If the SPI system is disabled, i.e.,

SPEN (SPCTL.6) = 0 (reset value), these pins are conﬁgured for port functions.

• SS is the optional slave select pin. In a typical conﬁguration, an SPI master asserts

one of its port pins to select one SPI device as the current slave. An SPI slave device

uses its SS pin to determine whether it is selected.

Typical connections are shown in Figure 17 through Figure 19.

Fig 16. SPI block diagram

002aaa900

CPU clock

DIVIDER

BY 4, 16, 64, 128

SELECT

CLOCK LOGIC

SPI CONTROL REGISTER

READ DATA BUFFER

8-BIT SHIFT REGISTER

SPI CONTROL

SPI STATUS REGISTER

SPI clock (master)

CONTROL

LOGIC

MISO

P2.3

MOSI

P2.2

SPICLK

P2.5

P2.4

SPI

interrupt

request

internal

data

bus

MSTR

SPEN

clock

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