MPR121 datasheet(48/57 Pages) FREESCALE

48 / 57 page

MPR121

Sensors

Freescale Semiconductor

BIT TRANSFER

One data bit is transferred during each clock pulse (Figure 50). The data on SDA must remain stable while SCL is high.

Figure 50. Bit Transfer

ACKNOWLEDGE

The acknowledge bit is a clocked 9th bit (Figure 51) which the recipient uses to handshake receipt of each byte of data. Thus

each byte transferred effectively requires 9 bits. The master generates the 9th clock pulse, and the recipient pulls down SDA

during the acknowledge clock pulse, such that the SDA line is stable low during the high period of the clock pulse. When the

master is transmitting to the MPR121, the MPR121 generates the acknowledge bit, since the MPR121 is the recipient. When the

MPR121 is transmitting to the master, the master generates the acknowledge bit, since the master is the recipient.

Figure 51. Acknowledge

THE SLAVE ADDRESS

The MPR121 has a 7-bit long slave address (Figure 52). The bit following the 7-bit slave address (bit eight) is the R/W bit, which

is low for a write command and high for a read command.

Figure 52. Slave Address

The MPR121 monitors the bus continuously, waiting for a START condition followed by its slave address. When a MPR121

recognizes its slave address, it acknowledges and is then ready for continued communication.

The MPR121 slave addresses are show in Table 46.

Table 46.

ADDR Pin Connection

I2C Address

VDD

0x4C

VSS

0x4D

SDA

0x4E

SCL

0x4F

START

CONDITION

SDA

SCL

STOP

CONDITION

START

CONDITION

SDA

BY TRANSMITTER

CLOCK PULSE FOR

ACKNOWLEDGEMENT

SDA

BY RECEIVER

SCL

SDA

R/W

ACK

MSB

SCL

MPR121 Datenblatt(PDF) 48 Page - Freescale Semiconductor, Inc

MPR121 Datenblatt(HTML) 48 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57

Datenblatt Download

Link URL