HT68F03 datasheet(86/139 Pages) HOLTEK

86 / 139 page

HT66F03/HT66F04/HT68F03/HT68F04

Rev. 1.00

April 16, 2010

Timer/Counter Mode

To select this mode, bits TnAM1, TnAM0 and TnBM1,

TnBM0 in the TMnC1 and TMnC2 register should all be

set high. The Timer/Counter Mode operates in an identi-

cal way to the Compare Match Output Mode generating

the same interrupt flags. The exception is that in the

Timer/Counter Mode the TM output pin is not used.

Therefore the above description and Timing Diagrams

for the Compare Match Output Mode can be used to un-

derstand its function. As the TM output pin is not used in

this mode, the pin can be used as a normal I/O pin or

other pin-shared function.

PWM Output Mode

To select this mode, the required bit pairs, TnAM1,

TnAM0 and TnBM1, TnBM0 should be set to 10 respec-

tively and also the TnAIO1, TnAIO0 and TnBIO1,

TnBIO0 bits should be set to 10 respectively. The PWM

function within the TM is useful for applications which re-

quire functions such as motor control, heating control, il-

lumination control etc. By providing a signal of fixed

frequency but of varying duty cycle on the TM output pin,

a square wave AC waveform can be generated with

varying equivalent DC RMS values.

As both the period and duty cycle of the PWM waveform

can be controlled, the choice of generated waveform is

extremely flexible. In the PWM mode, the TnCCLR bit is

used to determine in which way the PWM period is con-

trolled. With the TnCCLR bit set high, the PWM period

can be finely controlled using the CCRA registers. In this

case the CCRB registers are used to set the PWM duty

value (for TPnB output pin). The CCRP bits are not used

and TPnA output pin is not used. The PWM output can

only be generated on the TPnB output pin. With the

TnCCLR bit cleared to zero, the PWM period is set using

one of the eight values of the three CCRP bits, in multi-

ples of 128. Now both CCRA and CCRB registers can be

used to setup different duty cycle values to provide dual

PWM outputs on their relative TPnA and TPnB pins.

The TnPWM1 and TnPWM0 bits determine the PWM

alignment type, which can be either edge or centre type.

In edge alignment, the leading edge of the PWM signals

will all be generated concurrently when the counter is re-

set to zero. With all power currents switching on at the

same time, this may give rise to problems in higher

power applications. In centre alignment the centre of the

PWM active signals will occur sequentially, thus reduc-

ing the level of simultaneous power switching currents.

Interrupt flags, one for each of the CCRA, CCRB and

CCRP, will be generated when a compare match occurs

from either the Comparator A, Comparator B or Com-

parator P. The TnAOC and TnBOC bits in the TMnC1 and

TMnC2 register are used to select the required polarity of

the PWM waveform while the two TnAIO1, TnAIO0 and

TnBIO1, TnBIO0 bits pairs are used to enable the PWM

output or to force the TM output pin to a fixed high or low

level. The TnAPOL and TnBPOL bit are used to reverse

the polarity of the PWM output waveform.

· ETM, PWM Mode, Edge-aligned Mode, TnCCLR=0

CCRP

001b

010b

011b

100b

101b

110b

111b

000b

Period

128

256

384

512

640

768

896

1024

A Duty

CCRA

B Duty

CCRB

· ETM, PWM Mode, Edge-aligned Mode, TnCCLR=1

CCRA

511

512

1021

1022

1023

Period

511

512

1021

1022

1023

B Duty

CCRB

· ETM, PWM Mode, Center-aligned Mode, TnCCLR=0

CCRP

001b

010b

011b

100b

101b

110b

111b

000b

Period

256

512

768

1024

1280

1536

1792

2046

A Duty

(CCRA

´2)-1

B Duty

(CCRB

´2)-1

· ETM, PWM Mode, Center-aligned Mode, TnCCLR=1

CCRA

511

512

1021

1022

1023

Period

1022

1024

2042

2044

2046

B Duty

(CCRB

´2)-1

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