PIC18F23K20 datasheet(47/456 Pages) MICROCHIP

47 / 456 page

 2010 Microchip Technology Inc.

DS41303G-page 47

PIC18F2XK20/4XK20

3.4.1

PRI_IDLE MODE

This mode is unique among the three low-power Idle

modes, in that it does not disable the primary device

clock. For timing sensitive applications, this allows for

the fastest resumption of device operation with its more

accurate primary clock source, since the clock source

does not have to “warm-up” or transition from another

oscillator.

PRI_IDLE mode is entered from PRI_RUN mode by

setting the IDLEN bit and executing a SLEEP instruc-

tion. If the device is in another Run mode, set IDLEN

first, then clear the SCS bits and execute SLEEP.

Although the CPU is disabled, the peripherals continue

to be clocked from the primary clock source specified

by the FOSC<3:0> Configuration bits. The OSTS bit

remains set (see Figure 3.3).

When a wake event occurs, the CPU is clocked from the

primary clock source. A delay of interval TCSD is

required between the wake event and when code

execution starts. This is required to allow the CPU to

become ready to execute instructions. After the wake-

up, the OSTS bit remains set. The IDLEN and SCS bits

are not affected by the wake-up (see Figure 3-4).

3.4.2

SEC_IDLE MODE

In SEC_IDLE mode, the CPU is disabled but the

peripherals continue to be clocked from the Timer1

oscillator. This mode is entered from SEC_RUN by set-

ting the IDLEN bit and executing a SLEEP instruction. If

the device is in another Run mode, set the IDLEN bit

first, then set the SCS<1:0> bits to ‘01’ and execute

SLEEP

. When the clock source is switched to the

Timer1 oscillator, the primary oscillator is shut down,

the OSTS bit is cleared and the T1RUN bit is set.

When a wake event occurs, the peripherals continue to

be clocked from the Timer1 oscillator. After an interval

of TCSD following the wake event, the CPU begins exe-

cuting code being clocked by the Timer1 oscillator. The

IDLEN and SCS bits are not affected by the wake-up;

the Timer1 oscillator continues to run (see Figure 3-4).

FIGURE 3-3:

TRANSITION TIMING FOR ENTRY TO IDLE MODE

FIGURE 3-4:

TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE

Note:

The Timer1 oscillator should already be

running prior to entering SEC_IDLE mode.

If the T1OSCEN bit is not set when the

SLEEP

instruction is executed, the main

system clock will continue to operate in the

previously selected mode and the corre-

sponding IDLE mode will be entered (i.e.,

PRI_IDLE or RC_IDLE).

Peripheral

Program

PC + 2

OSC1

CPU Clock

Clock

Counter

OSC1

Peripheral

Program

CPU Clock

Clock

Counter

Wake Event

TCSD

PIC18F23K20 Datenblatt(PDF) 47 Page - Microchip Technology

PIC18F23K20 Datenblatt(HTML) 47 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datenblatt Download

Link URL