PIC24F16KA102 datasheet(92/254 Pages) MICROCHIP

92 / 254 page

PIC24F16KA102 FAMILY

DS39927B-page 90

Preliminary

8.4

Interrupt Setup Procedures

8.4.1

INITIALIZATION

To configure an interrupt source:

Set the NSTDIS Control bit (INTCON1<15>) if

nested interrupts are not desired.

Select the user-assigned priority level for the

interrupt source by writing the control bits in the

appropriate IPCx register. The priority level will

depend on the specific application and type of

interrupt source. If multiple priority levels are not

desired, the IPCx register control bits for all

enabled interrupt sources may be programmed

to the same non-zero value.

Clear the interrupt flag status bit associated with

the peripheral in the associated IFSx register.

Enable the interrupt source by setting the

interrupt enable control bit associated with the

source in the appropriate IECx register.

8.4.2

INTERRUPT SERVICE ROUTINE

The method that is used to declare an ISR and initialize

the IVT with the correct vector address depends on the

programming language (i.e., C or assembler) and the

language development toolsuite that is used to develop

the application. In general, the user must clear the

interrupt flag in the appropriate IFSx register for the

source of the interrupt that the ISR handles. Otherwise,

the ISR will be re-entered immediately after exiting the

routine. If the ISR is coded in assembly language, it

must be terminated using a RETFIE instruction to

unstack the saved PC value, SRL value and old CPU

priority level.

8.4.3

TRAP SERVICE ROUTINE (TSR)

A Trap Service Routine (TSR) is coded like an ISR,

except that the appropriate trap status flag in the

INTCON1 register must be cleared to avoid re-entry

into the TSR.

8.4.4

INTERRUPT DISABLE

All user interrupts can be disabled using the following

procedure:

Push the current SR value onto the software

stack using the PUSH instruction.

Force the CPU to priority level 7 by inclusive

ORing the value OEh with SRL.

To enable user interrupts, the POP instruction may be

used to restore the previous SR value.

Only user interrupts with a priority level of 7 or less can

be disabled. Trap sources (level 8-15) cannot be

disabled.

The DISI instruction provides a convenient way to

disable interrupts of priority levels 1-6 for a fixed period.

Level 7 interrupt sources are not disabled by the DISI

instruction.

Note:

At a device Reset, the IPCx registers are

initialized, such that all user interrupt

sources are assigned to priority level 4.

PIC24F16KA102 Datenblatt(PDF) 92 Page - Microchip Technology

PIC24F16KA102 Datenblatt(HTML) 92 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datenblatt Download

Link URL