PIC16F1934-ESLASHML datasheet(78/418 Pages) MICROCHIP

78 / 418 page

PIC16F193X/LF193X

DS41364A-page 76

Preliminary

4.5.4

PIE3 REGISTER

The PIE3 register contains the interrupt enable bits, as

shown in Register 4-4.

Note:

Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3

U-0

R/W-0/0

U-0

R/W-0/0

U-0

—

CCP5IE

CCP4IE

CCP3IE

TMR6IE

—TMR4IE

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7

Unimplemented: Read as ‘0’

bit 6

CCP5IE: CCP5 Interrupt Enable bit

= Enables the CCP5 interrupt

= Disables the CCP5 interrupt

bit 5

CCP4IE: CCP4 Interrupt Enable bit

= Enables the CCP4 interrupt

= Disables the CCP4 interrupt

bit 4

CCP3IE: CCP3 Interrupt Enable bit

= Enables the CCP3 interrupt

= Disables the CCP3 interrupt

bit 3

TMR6IE: TMR6 to PR6 Match Interrupt Enable bit

= Enables the TMR6 to PR6 Match interrupt

= Disables the TMR6 to PR6 Match interrupt

bit 2

Unimplemented: Read as ‘0’

bit 1

TMR4IE: TMR4 to PR4 Match Interrupt Enable bit

= Enables the TMR4 to PR4 Match interrupt

= Disables the TMR4 to PR4 Match interrupt

bit 0

Unimplemented: Read as ‘0’

PIC16F1934-E/ML Datenblatt(PDF) 78 Page - Microchip Technology

PIC16F1934-E/ML Datenblatt(HTML) 78 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datenblatt Download

Link URL