MIC2165 datasheet(13/27 Pages) MICREL

13 / 27 page

Micrel, Inc.

MIC2165

June 2010

M9999-060810-D

at startup by controlling the output voltage rise time. The

input surge appears while the output capacitor is

charged up. A slower output rise time will draw a lower

input surge current.

The MIC2165 implements an internal digital soft-start by

making the 0.8V reference voltage VREF ramp from 0 to

100% in about 5ms. Therefore, the output voltage is

controlled to increase slowly by a stair-case VREF ramp.

Once the soft-start cycle ends, the related circuitry is

disabled to reduce current consumption. During soft-start,

the discontinuous mode is disabled in MIC2165.

Current Limit

The MIC2165 uses the RDS(ON) of the low-side power

MOSFET to sense over-current conditions. This method

will avoid adding cost, board space and power losses

taken by discrete current sense resistors. The low-side

MOSFET is used because it displays much lower

parasitic oscillations during switching than the high-side

MOSFET.

In each switching cycle of the MIC2165 converter, the

inductor current is sensed by monitoring the low-side

MOSFET in the OFF period. The sensed voltage is

compared with a current-limit threshold voltage VCL after

a blanking time of 150ns. If the sensed voltage is over

VCL, which is 133mV typical at 0.8V VFB, then the

MIC2165 turns off the high-side and low-side MOSFETs

and a soft-start sequence is triggered. This mode of

operation is called “hiccup mode” and its purpose is to

protect the downstream load in case of a hard short. The

current limit threshold VCL has a foldback characteristic

related to the FB voltage. Please refer to the “Typical

Characteristics” for the curve of current limit threshold vs.

FB voltage percentage. The circuit in Figure 5 illustrates

the MIC2165 current limiting circuit.

Figure 5. MIC2165 Current Limiting Circuit

Using the typical VCL value of 133mV, the current limit

value is roughly estimated as:

DS(ON)

133mV

≈

For designs where the current ripple is significant

compared to the load current IOUT, or for low duty-cycle

operation, calculating the current limit ICL should take

into account that one is sensing the peak inductor

current and that there is a blanking delay of

approximately 150ns.

ΔI

133mV

L(PP)

DLY

OUT

DS(ON)

−

(2)

ΔI

OUT

L(PP)

−

(3)

where:

VOUT = The output voltage

tDLY = Current limit blanking time, 150ns typical

ΔIL(PP) = Inductor current ripple peak-to-peak value

D = Duty Cycle

fSW = Switching frequency

The MOSFET RDS(ON) varies between 30% to 40% with

temperature; therefore, it is recommended to add 50%

margin to ICL in the above equation to avoid false current

limiting due to increased MOSFET junction temperature

rise. It is also recommended to connect SW pin directly

to the drain of the low-side MOSFET to accurately sense

the MOSFETs RDS(ON).

MOSFET Gate Drive

The MIC2165 high-side drive circuit is designed to

switch an N-Channel MOSFET. The typical application

schematic shows a bootstrap circuit, consisting of D1 (a

Schottky diode is recommended) and CBST. This circuit

supplies energy to the high-side drive circuit. Capacitor

CBST is charged while the low-side MOSFET is on and

the voltage on the SW pin is approximately 0V. When

the high-side MOSFET driver is turned on, energy from

CBST is used to turn the MOSFET on. As the high-side

MOSFET turns on, the voltage on the SW pin increases

to approximately VIN. Diode D1 is reversed biased and

CBST floats high while continuing to keep the high-side

MOSFET on. The bias current of the high-side driver is

less than 10mA so a 0.1μF to 1μF is sufficient to hold

the gate voltage with minimal droop for the power stroke

(high-side switching) cycle, i.e., ΔBST = 10mA x

1.67μs/0.1μF = 167mV. When the low-side MOSFET is

turned back on, CBST is recharged through D1. A small

resistor RG at BST pin can be used to slow down the

turn-on time of the high-side N-channel MOSFET.

The drive voltage is derived from the internal linear

regulator VDD. The nominal low-side gate drive voltage is

VDD and the nominal high-side gate drive voltage is

approximately VDD – VDIODE, where VDIODE is the voltage

drop across D1. A dead time of approximate 30ns delay

between the high-side and low-side driver transitions is

used to prevent current from simultaneously flowing

unimpeded through both MOSFETs.

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